초록 ▼

An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a histogram-based automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit and a digital g

An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a histogram-based automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit and a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.

대표청구항 ▼

What is claimed is: 1. A processing system for an imager device comprising: a camera system for producing an imager signal; a correlated double sample (CDS) circuit for receiving data from an imager; said correlated double sample circuit being adapted for variable gain amplification; an analog-to-d

What is claimed is: 1. A processing system for an imager device comprising: a camera system for producing an imager signal; a correlated double sample (CDS) circuit for receiving data from an imager; said correlated double sample circuit being adapted for variable gain amplification; an analog-to-digital converter (ADC) coupled to said CDS circuit; a digital gain circuit (DGC) coupled to said ADC; and histogram-based automatic gain control (AGC) circuit coupled to said DGC, effective for controlling said CDS circuit and said DGC, wherein said histogram-based AGC circuit generates error codes with histogram bins. 2. A processing system according to claim 1 comprising a timing generator for OFD pulses. 3. A processing system according to claim 1 comprising a timing generator. 4. A processing system according to claim 1, wherein said histogram-based AGC circuit is effective for controlling the gain of said camera system. 5. A processing system according to claim 4, wherein said histogram-based AGC circuit is effective for controlling a timing circuit. 6. A processing system according to claim 5, wherein said timing circuit controls shutter gain. 7. A processing system according to claim 1 including a read only memory (ROM) and a multiplier effective for multiplying an ADC output with a selected copy multiplicand from said ROM. 8. A processing system according to claim 1 wherein said histogram-based AGC circuit generates error codes with histogram bins by: setting a target level for various histogram bins, storing information about pixel intensities for a selected frame according to the histogram bins set to selected different pixel intensities for providing overall brightness of the selected frame, and determining whether to increment, decrement, or maintain a current gain level which adjusts the overall brightness of the selected frame based on which bin is a highest level bin among the various histogram bins having a pixel level to exceed said target level. 9. A processing method for an imager device comprising: producing, by a camera system, an imager signal; receiving data, by a correlated double sample (CDS) circuit, from an imager; adapting said correlated double sample circuit for variable gain amplification wherein an analog-to-digital converter (ADC) is coupled to said CDS circuit, a digital gain circuit (DGC) is coupled to said ADC, and histogram-based automatic gain control (AGC) circuit is coupled to said DGC, generating, by said histogram-based AGC circuit, error codes with histogram bins, and effectively controlling, by said histogram-based AGC circuit, said CDS circuit and said DGC. 10. A processing method according to claim 9 further comprising: generating timing, by a timing generator, for OFD pulses. 11. A processing method according to claim 9 further comprising: generating timing by a timing generator. 12. A processing method according to claim 9, wherein effectively controlling, by said histogram-based AGC circuit, said CDS circuit and said DGC further comprises: effectively controlling, by said histogram-based AGC circuit, the gain of said camera system. 13. A processing method according to claim 12, wherein effectively controlling, by said histogram-based AGC circuit, said CDS circuit and said DGC further comprises: effectively controlling, by said histogram-based AGC circuit, a timing circuit. 14. A processing method according to claim 13, further comprising: controlling, by said timing circuit, shutter gain. 15. A processing method according to claim 9 further comprising: effectively multiplying, by a multiplier, an ADC output with a selected copy multiplicand from a read only memory (ROM). 16. A processing method according to claim 9, wherein generating, by said histogram-based AGC circuit, error codes with histogram bins further comprises: setting a target level for various histogram bins; storing information about pixel intensities for a selected frame according to the histogram bins set to selected different pixel intensities for providing overall brightness of the selected frame; and determining whether to increment, decrement, or maintain a current gain level which adjusts the overall brightness of the selected frame based on which bin is a highest level bin among the various histogram bins having a pixel level to exceed said target level.