Non-Circular via holes for bumping pads and related structures
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-023/48
H01L-023/52
H01L-029/40
출원번호
UP-0270366
(2005-11-09)
등록번호
US-7531898
(2009-07-01)
발명자
/ 주소
Batchelor, William E.
Rinne, Glenn A.
출원인 / 주소
Unitive International Limited
대리인 / 주소
Myers Bigel Sibley & Sajovec, P.A.
인용정보
피인용 횟수 :
5인용 특허 :
169
초록▼
An integrated circuit device may include a substrate, a conductive pad on a surface of the substrate, and a conductive line on the surface of the substrate. Moreover, the conductive line may be connected to the conductive pad, and the conductive line may be narrow relative to the conductive pad. In
An integrated circuit device may include a substrate, a conductive pad on a surface of the substrate, and a conductive line on the surface of the substrate. Moreover, the conductive line may be connected to the conductive pad, and the conductive line may be narrow relative to the conductive pad. In addition, an insulating layer may be provided on the substrate, on the conductive line, and on edge portions of the conductive pad. The insulating layer may have a hole therein exposing a central portion of the conductive pad, and a first segment of a perimeter of the hole may substantially define an arc of a circle around the central portion of the conductive pad. A second segment of the perimeter of the hole may substantially deviate from the circle around the central portion of the conductive pad, and the second segment of the perimeter of the hole may be adjacent a connection between the conductive line and the conductive pad.
대표청구항▼
That which is claimed is: 1. An integrated circuit device comprising: a substrate; a conductive pad on a surface of the substrate; a conductive line on the surface of the substrate wherein the conductive line is connected to the conductive pad and wherein the conductive line is narrow relative to t
That which is claimed is: 1. An integrated circuit device comprising: a substrate; a conductive pad on a surface of the substrate; a conductive line on the surface of the substrate wherein the conductive line is connected to the conductive pad and wherein the conductive line is narrow relative to the conductive pad in a direction parallel with respect to the surface of the substrate; and an insulating layer on the substrate, on the conductive line, and on edge portions of the conductive pad wherein the insulating layer has a hole therein exposing a central portion of the conductive pad, and wherein a first segment of a perimeter of the hole substantially defines an arc of a circle around the central portion of the conductive pad and wherein a second segment of the perimeter of the hole substantially deviates from the circle around the central portion of the conductive pad, and wherein the second segment of the perimeter of the hole is adjacent a connection between the conductive line and the conductive pad. 2. An integrated circuit device according to claim 1 further comprising: a conductive bump on the central portion of the conductive pad and on portions of the insulating layer surrounding the hole so that the insulating layer is between the conductive bump and edge portions of the conductive pad. 3. An integrated circuit device according to claim 2 wherein the conductive bump comprises a solder bump. 4. An integrated circuit device according to claim 2 wherein the conductive bump has a substantially circular footprint on the insulating layer. 5. An integrated circuit device according to claim 2 further comprising: an underbump metallurgy layer on the central portion of the conductive pad and on portions of the insulating layer surrounding the hole so that the under bump metallurgy layer is between the conductive bump and portions of the insulating layer surrounding the hole, and wherein the underbump metallurgy layer and the conductive bump comprise different materials. 6. An integrated circuit device according to claim 1 wherein the substrate comprises a semiconductor substrate having opposing first and second surfaces and wherein the conductive pad, the conductive line, and the insulating layer are on the first surface, wherein the conductive line and the edge portions of the conductive pad are between the insulating layer and the first surface, the integrated circuit device further comprising: an input/output pad on the substrate wherein the conductive line provides electrical connection between the conductive pad and the input/output pad. 7. An integrated circuit device according to claim 6 wherein the conductive line comprises a first conductive line directly connected to the input/output pad, the integrated circuit device further comprising: a second conductive line of the first surface of the semiconductor substrate wherein the second conductive line is directly connected to the input/output pad; a second conductive pad on the first surface of the semiconductor substrate wherein the second conductive pad is directly connected to the second conductive line wherein the insulating layer has a second hole therein exposing a central portion of the second conductive pad; a first conductive bump on the central portion of the first conductive pad and on portions of the insulating layer surrounding the first hole; and a second conductive bump on the central portion of the second conductive pad and on portions of the insulating layer surrounding the second hole. 8. An integrated circuit device according to claim 1 wherein the second segment of the perimeter of the hole substantially defines a line. 9. An integrated circuit device according to claim 8 wherein a length of the second segment is at least as great as a width of the conductive line. 10. An integrated circuit device according to claim 1 wherein the second segment of the perimeter of the hole curves toward the center of the conductive pad. 11. An integrated circuit device comprising: a substrate having first and second opposing surfaces; a conductive pad on the first surface of the substrate; a conductive line on the first surface of the substrate wherein the conductive line is connected to the conductive pad and wherein the conductive line is narrow relative to the conductive pad; an insulating layer on the first surface of the substrate, on the conductive line, and on edge portions of the conductive pad wherein the insulating layer has a hole therein exposing a central portion of the conductive pad and wherein at least a segment of a perimeter of the hole is non-circular and wherein the perimeter of the hole is defined in a plane parallel with respect to the first surface of the substrate; and a conductive bump on the central portion of the conductive pad and on portions of the insulating layer surrounding the hole so that the insulating layer is between the conductive bump and edge portions of the conductive pad and wherein the conductive bump has a substantially circular footprint on the insulating layer. 12. An integrated circuit device according to claim 11 wherein the conductive bump comprises a solder bump. 13. An integrated circuit device according to claim 11 further comprising: an underbump metallurgy layer on the central portion of the conductive pad and on portions of the insulating layer surrounding the hole so that the under bump metallurgy layer is between the conductive bump and portions of the insulating layer surrounding the hole, and wherein the underbump metallurgy layer and the conductive bump comprise different materials. 14. An integrated circuit device according to claim 11 wherein a first segment of a perimeter of the hole substantially defines an arc of a circle around the central portion of the conductive pad and wherein a second segment of the perimeter of the hole substantially deviates from the circle around the central portion of the conductive pad. 15. An integrated circuit device according to claim 14 wherein the second segment of the perimeter of the hole is adjacent a connection between the conductive line and the conductive pad. 16. An integrated circuit device according to claim 14 wherein the second segment of the perimeter of the hole substantially defines a line. 17. An integrated circuit device according to claim 16 wherein a length of the second segment is at least as great as a width of the conductive line. 18. An integrated circuit device according to claim 14 wherein the second segment of the perimeter of the hole curves toward the center of the conductive pad. 19. An integrated circuit device according to claim 11 wherein the substrate comprises a semiconductor substrate, the integrated circuit device further comprising: an input/output pad on the first surface of the semiconductor substrate wherein the conductive line provides electrical connection between the conductive pad and the input/output pad. 20. An integrated circuit device according to claim 19 wherein the conductive line comprises a first conductive line directly connected to the input/output pad, the integrated circuit device further comprising: a second conductive line on the first surface of the semiconductor substrate wherein the second conductive line is directly connected to the input/output pad; a second conductive pad directly connected to the second conductive line wherein the insulating layer has a second hole therein exposing a central portion of the second conductive pad wherein edge portions of the first and second conductive pads are between the insulating layer and the first surface of the semiconductor substrate; a first conductive bump on the central portion of the first conductive pad and on portions of the insulating layer surrounding the first hole; and a second conductive bump on the central portion of the second conductive pad and on portions of the insulating layer surrounding the second hole. 21. An integrated circuit device comprising a semiconductor substrate having first and second opposing surfaces; an input/output pad on the first surface of the semiconductor substrate; first and second conductive lines on the first surface of the semiconductor substrate wherein both of the first and second conductive lines are directly connected to the input/output pad; first and second conductive pads on the first surface of the semiconductor substrate wherein the first conductive pad is directly connected to the first conductive line and wherein the second conductive pad is directly connected to the second conductive line; an insulating layer on the first and second conductive lines and on edge portions of the first and second conductive pads wherein the insulating layer has first and second holes therein exposing central portions of the respective first and second conductive pads so that the edge portions of the first and second conductive pads are between the insulating layer and the semiconductor substrate; a first conductive bump on the central portion of the first conductive bump and on portions of the insulating layer surrounding the first hole; and a second conductive bump on the central portion of the second conductive pad and on portions of the insulating layer surrounding the second hole. 22. An integrated circuit device according to claim 21 wherein the first and second conductive bumps comprise respective first and second solder bumps. 23. An integrated circuit device according to claim 21 wherein each of the first and second conductive bumps has a substantially circular footprint on the insulating layer. 24. An integrated circuit device according to claim 21 further comprising: a first underbump metallurgy layer on the central portion of the first conductive pad and on portions of the insulating layer surrounding the first hole so that the first under bump metallurgy layer is between the first conductive bump and portions of the insulating layer surrounding the first hole wherein the first underbump metallurgy layer and the first conductive bump comprise different materials; and a second underbump metallurgy layer on the central portion of the second conductive pad and on portions of the insulating layer surrounding the second hole so that the second under bump metallurgy layer is between the second conductive bump and portions of the insulating layer surrounding the second hole wherein the second underbump metallurgy layer and the second conductive bump comprise different materials. 25. An integrated circuit device according to claim 21 wherein the first conductive line provides a first electrical resistance between the input/output pad and the first conductive pad, wherein the second conductive line provides a second electrical resistance between the input/output pad and the second conductive pad, and wherein the first and second electrical resistances are different. 26. An integrated circuit device according to claim 25 wherein the first conductive line has a first length between the input/output pad and the first conductive pad, wherein the second conductive line has a second length between the input/output pad and the second conductive pad, and wherein the first and second lengths are different. 27. An integrated circuit device according to claim 25 wherein the first conductive line has a first width, wherein the second conductive line has a second width, and wherein the first and second widths are different. 28. An integrated circuit device according to claim 25 wherein the first conductive line has a first thickness, wherein the second conductive line has a second thickness, and wherein the first and second thicknesses are different. 29. An integrated circuit device according to claim 25 wherein the first conductive line comprises a first material, wherein the second conductive line comprises a second material, and wherein the first and second materials are different. 30. An integrated circuit device according to claim 21 wherein the input/output pad comprises a ground pad providing a ground connection for the integrated circuit device. 31. An integrated circuit device according to claim 21 wherein the input/output pad comprises a power pad providing a power connection for the integrated circuit device. 32. An integrated circuit device according to claim 21 wherein the first conductive line is narrow relative to the first conductive pad, and wherein a first segment of a perimeter of the first hole substantially defines an arc of a circle around the central portion of the first conductive pad and wherein a second segment of the perimeter of the first hole substantially deviates from the circle around the central portion of the conductive pad, wherein the second segment of the perimeter of the first hole is adjacent a connection between the conductive line and the conductive pad, and wherein the perimeter of the first hole is defined in a plane parallel with respect to the first surface of the substrate. 33. An integrated circuit device according to claim 21 wherein at least a segment of a perimeter of the first hole is non-circular. 34. An integrated circuit device according to claim 21 wherein the first and second conductive lines are configured such that the first conductive bump fails due to electromigration before the second conductive bump fails. 35. An integrated circuit device according to claim 1 wherein the substrate comprises a semiconductor substrate. 36. An integrated circuit device according to claim 35 wherein the conductive line is narrow relative to the conductive pad in a dimension parallel with respect to a surface of the semiconductor substrate, and wherein the perimeter of the hole including the first and second segments is defined in a plane parallel with respect to the surface of the semiconductor substrate. 37. An integrated circuit device according to claim 11 wherein the substrate comprises a semiconductor substrate. 38. An integrated circuit device according to claim 3 wherein the solder bump comprises lead-tin solder, lead-bismuth solder, lead-indium solder, tin-silver solder, tin-silver-copper solder, indium-tin solder, indium-gallium solder, gallium solder, indium-bismuth solder, tin-bismuth solder, indium-cadmium solder, bismuth-cadmium solder, and/or tin-cadmium solder. 39. An integrated circuit device according to claim 12 wherein the solder bump comprises lead-tin solder, lead-bismuth solder, lead-indium solder, tin-silver solder, tin-silver-copper solder, indium-tin solder, indium-gallium solder, gallium solder, indium-bismuth solder, tin-bismuth solder, indium-cadmium solder, bismuth-cadmium solder, and/or tin-cadmium solder. 40. An integrated circuit device according to claim 22 wherein each of the first and second solder bumps comprises lead-tin solder, lead-bismuth solder, lead-indium solder, tin-silver solder, tin-silver-copper solder, indium-tin solder, indium-gallium solder, gallium solder, indium-bismuth solder, tin-bismuth solder, indium-cadmium solder, bismuth-cadmium solder, and/or tin-cadmium solder.
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