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A memory module adapted for installation in an open memory socket on a mainboard of a computer. The memory module includes a substrate with an edge connector comprising pins along an edge of the substrate, and at least one memory package mounted to the substrate and containing a memory die electrica

A memory module adapted for installation in an open memory socket on a mainboard of a computer. The memory module includes a substrate with an edge connector comprising pins along an edge of the substrate, and at least one memory package mounted to the substrate and containing a memory die electrically connected to input/output leads located along the perimeter of the memory package and through which data signals are transmitted to and from the memory die. Data signal lines electrically connect a plurality of the input/output leads of the memory package to a plurality of the pins of the edge connector. Termination resistors individually electrically connect each of the data signal lines to ground, a supply voltage, or a reference voltage of the memory package so as to reduce noise and signal reflections through the data signal lines.

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What is claimed is: 1. A memory module installed in a memory socket on a mainboard of a computer, the memory module comprising: a substrate; an edge connector comprising pins along an edge of the substrate; multiple memory packages mounted to the substrate, each of the memory packages containing a

What is claimed is: 1. A memory module installed in a memory socket on a mainboard of a computer, the memory module comprising: a substrate; an edge connector comprising pins along an edge of the substrate; multiple memory packages mounted to the substrate, each of the memory packages containing a memory die electrically connected to input/output leads located on the memory package and through which data signals are transmitted to and from the memory die; data signal lines electrically connecting a plurality of the input/output leads of the memory package to a plurality of the pins of the edge connector; and termination resistors mounted on each of the memory packages and individually terminating each of the input/output leads of each memory package to a supply voltage or a reference voltage of the memory package; wherein the memory die and the mainboard lack termination resistors, and the termination resistors operate to reduce noise and signal reflections through the data signal lines. 2. The memory module according to claim 1, further comprising a switch operable to dynamically couple and decouple the termination resistors according to whether a physical bank of memory is active or not. 3. The memory module according to claim 1, wherein the memory module is chosen from the group consisting of single in-line memory modules and dual in-line memory modules. 4. The memory module according to claim 1, wherein the memory packages are chosen from the group consisting of DRAM, SDR SDRAM, and DDR SDRAM chips. 5. The memory module according to claim 1, wherein the termination resistors are electrically connected to the supply voltage. 6. The memory module according to claim 1, wherein the termination resistors are electrically connected to the reference voltage. 7. The memory module according to claim 1, wherein the termination resistors are terminated to the reference voltage and operate to assist high and low signal voltages to return to a crossover point of the memory package via a push-pull mechanism for the voltage swing. 8. The memory module according to claim 1, wherein the termination resistors are terminated to the supply voltage and compensate for asymmetries in the high-low voltage swing of the memory package. 9. The memory module according to claim 1, wherein the termination resistors are connected to the supply voltage or the reference voltage through a conducting plane on the memory package. 10. The memory module according to claim 1, wherein the termination resistors are terminated to a virtual termination voltage that differs from the reference voltage of the memory package and is adjusted above and below the reference voltage to compensate for asymmetries in the high-low voltage swing of the memory package.