초록 ▼

The encoder chip of the present invention uses LDPC codes to encode input message data at a transmitting end, thereby generating a series of codewords. The encoder chip implements two low-density parity-check (LDPC) codes. The first LDPC code is a (4088,3360) code (4K) which is shortened from a (409

The encoder chip of the present invention uses LDPC codes to encode input message data at a transmitting end, thereby generating a series of codewords. The encoder chip implements two low-density parity-check (LDPC) codes. The first LDPC code is a (4088,3360) code (4K) which is shortened from a (4095,3367) cyclic code. The second LDPC code is a quasi-cyclic (8158,7136) code (8K). The message data and the generated codewords are transmitted to a receiving end where the received codewords are decoded and checked for errors. To generate the codewords, the encoder applies a generator matrix G to the input message data. The G matrix is generated by first defining an H matrix. An H matrix is initially defined as 16×2 array of right-circulant sub-matrices. The G matrix is formed by manipulating the H matrix according to a 4-step algorithm. A randomizer and a synchronization marker are also included within the encoder.

대표청구항 ▼

We claim: 1. A method of encoding data, the method comprising: a. defining an H matrix, wherein the H matrix comprises a plurality of sub-matrices configured as rows and columns, each sub-matrix comprising a circulant matrix, and wherein the H matrix is defined according to a (8158,7136) low-densit

We claim: 1. A method of encoding data, the method comprising: a. defining an H matrix, wherein the H matrix comprises a plurality of sub-matrices configured as rows and columns, each sub-matrix comprising a circulant matrix, and wherein the H matrix is defined according to a (8158,7136) low-density parity check code; b. shifting each column of the H matrix by two columns to the right, thereby forming an H' matrix; c. forcing the H' matrix into upper triangular form; d. making a last row of the upper triangular form H' matrix circular, thereby forming an H" matrix; e. determining a parity matrix P according to P=P'T, wherein P'T is determined according to H"=[I:P']; f. generating a generator matrix G according to G=[I:P]; and g. encoding the data according to the generator matrix G. 2. The method according to claim 1 wherein the last row of the upper triangular form H' matrix comprises row 1022. 3. The method according to claim 1 wherein each circulant matrix within the H matrix comprises a right-circulant matrix. 4. The method according to claim 1 wherein the H matrix comprises 32 right-circulant matrices. 5. The method according to claim 1 wherein each circulant matrix within the H matrix comprises a 511×511 right-circulant matrix. 6. The method according to claim 5 wherein each 511×511 right-circulant matrix includes two ones per row and two ones per column. 7. The method according to claim 1 wherein the H matrix comprises a 2×16 array of right-circulant matrices. 8. The method according to claim 1 wherein the (8158,7136) low-density parity check code is shortened from a (8176,7154) quasi-cyclic low-density parity check code. 9. The method according to claim 1 wherein each circulant matrix comprises a 512×512 right-circulant matrix. 10. The method according to claim 9 wherein each 512×512 right-circulant matrix includes one per row and one per column. 11. The method according to claim 9 wherein the H matrix is configured as a 4×32 array of the 512×512 right-circulant matrices. 12. The method according to claim 1 wherein each circulant matrix is configured differently. 13. An encoder to provide parity data, the encoder comprising: a. an input register to receive input data; b. a parity generator coupled to receive the input data from the input register, wherein the parity generator generates parity data according to a G matrix, further wherein the parity generator generates the G matrix by defining an H matrix, wherein the H matrix comprises a plurality of sub-matrices configured as rows and columns and the H matrix is defined according to a (8158,7136) low-density parity check code, each sub-matrix comprising a circulant matrix, shifting each column of the H matrix by two columns to the right, thereby forming an H' matrix, forcing the H' matrix into upper triangular form, making a last row of the upper triangular form H' matrix circular, thereby forming an H" matrix, determining a parity matrix P according to P=P'T, wherein P'T is determined according to H"=[I:P'], and generating the G matrix according to G=[I:P]; and c. an output circuit to output the input data received from the input register and the parity data received from the parity generator. 14. The encoder according to claim 13 wherein the output circuit comprises a multiplexor. 15. The encoder according to claim 13 further comprising a randomizer coupled to receive and to randomize the input data and the parity data. 16. The encoder according to claim 13 further comprising a bit packer coupled to receive the input data from the input register and to output a data packet. 17. The encoder according to claim 16 wherein the bit packer comprises a 16-bit to 21-bit packer and the data packet comprises a 21-bit data packet. 18. The encoder according to claim 16 further comprising a bit unpacker coupled to receive the data packet from the bit packer and to reformat the data packet at a boundary between two of the circulant matrices. 19. The encoder according to claim 18 wherein the bit unpacker comprises a 21-bit to 7-bit unpacker. 20. The encoder according to claim 13 wherein the parity generator comprises a generator coefficient read-only-memory, a multiply-accumulate block, and a parity register. 21. The encoder according to claim 20 wherein the parity generator further comprises a generator polynomial register. 22. The encoder according to claim 13 wherein the parity generator comprises an 8 k parity generator. 23. The encoder according to claim 13 wherein the parity generator comprises two independent parity generators. 24. The encoder according to claim 23 wherein the two parity generators comprise an 8 k parity generator and a 4 k parity generator. 25. The encoder according to claim 13 wherein the last row of the upper triangular form H' matrix comprises row 1022. 26. The encoder according to claim 13 wherein each circulant matrix within the H matrix comprises a right-circulant matrix. 27. The encoder according to claim 13 wherein the H matrix comprises 32 right-circulant matrices. 28. The encoder according to claim 13 wherein each circulant matrix within the H matrix comprises a 511×511 right-circulant matrix. 29. The encoder according to claim 28 wherein each 511×511 right-circulant matrix includes two ones per row and two ones per column. 30. The encoder according to claim 13 wherein the H matrix comprises a 2×16 array of right-circulant matrices. 31. The method according to claim 13 wherein the (8158,7136) low-density parity check code is shortened from a (8176,7154) quasi-cyclic low-density parity check code. 32. The encoder according to claim 13 wherein each circulant matrix comprises a 512×512 right-circulant matrix. 33. The encoder according to claim 32 wherein each 512×512 right-circulant matrix includes one per row and one per column. 34. The encoder according to claim 32 wherein the H matrix is configured as a 4×32 array of the 512×512 right-circulant matrices. 35. The encoder according to claim 13 wherein each circulant matrix is configured differently. 36. A parity generator for generating parity data, the parity Comprising: a. a bit packer configured to receive a data stream as a series of n-bit words to package the n-bit words into m-bit words according to a multi-state machine, and to output a stream of the m-bit words, wherein each data block of the stream is defined by a data block boundary and includes a plurality of m-bit words; b. a bit unpacker configured to receive the stream of m-bit words from the bit packer the bit unpacker including a word counter configured to determine and flag an m-bit word corresponding to a data block boundary of a data block, the bit unpacker further configured to adjust a data flow rate of the flagged m-bit word corresponding to the data block boundary, wherein the flagged m-bit word is the last m-bit word in the block; c. a memory to store a first row of a generator matrix; d. a multiply-accumulate arithmetic unit to apply the first row of the generator matrix to a first message data thereby generating a first codeword of parity data; e. parity register to receive the first codeword of parity data from the multiply-accumulate arithmetic unit; and f. a shadow register to store a specified number of most significant bits from the first codeword of message data in the parity register, wherein the specified number of most significant bits in the shadow register enables the multiply-accumulate arithmetic unit to apply a second row of the generator matrix to the first message data to generate a second codeword of parity data while the first codeword of parity data to generate a second codeword of parity data while the first codeword of parity data is shifted out of the parity register. 37. The parity generator of claim 36 wherein the multiply-accumulate arithmetic unit is programmable. 38. An encoder to provide parity data, he encoder comprising: a. an input register to receive input data; b. a parity generator coupled to receive the input data from the input register, wherein the parity generator generates parity data according to a G matrix, further wherein the parity generator generates the G matrix by defining an H matrix, wherein the H matrix comprises a plurality of sub-matrices configured as rows and columns and the H matrix is defined according to a (8158, 7136) low-density parity check code, each sub-matrix comprising a circulant matrix, shifting each column of the H matrix by two columns to the right, thereby forming an H' matrix, forcing the H' matrix into upper triangular form, making a last row of the upper triangular form H' matrix circular, thereby forming an H" matrix, determining a parity matrix P according to P=P'^T, wherein P'^T is determined according to H"=[I:P'], and generating the G matrix according to G=[I:P] and c. an output circuit to output the input data received from the input register and the parity data received from the parity generator.