[미국특허]
Binary group III-nitride based high electron mobility transistors
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-029/06
H01L-029/02
H01L-031/0328
H01L-031/0264
H01L-031/0336
H01L-031/072
H01L-031/06
H01L-031/109
H01L-031/102
출원번호
UP-0118675
(2005-04-29)
등록번호
US-7544963
(2009-07-01)
발명자
/ 주소
Saxler, Adam William
출원인 / 주소
Cree, Inc.
대리인 / 주소
Myers Bigel Sibley & Sajovec
인용정보
피인용 횟수 :
107인용 특허 :
66
초록▼
Binary Group III-nitride high electron mobility transistors (HEMTs) and methods of fabricating binary Group III-nitride HEMTs are provided. In some embodiments, the binary Group III-nitride HEMTs include a first binary Group III-nitride barrier layer, a binary Group III-nitride channel layer on the
Binary Group III-nitride high electron mobility transistors (HEMTs) and methods of fabricating binary Group III-nitride HEMTs are provided. In some embodiments, the binary Group III-nitride HEMTs include a first binary Group III-nitride barrier layer, a binary Group III-nitride channel layer on the first barrier layer; and a second binary Group III-nitride barrier layer on the channel layer. In some embodiments, the binary Group III-nitride HEMTs include a first AIN barrier layer, a GaN channel layer and a second AIN barrier layer.
대표청구항▼
That which is claimed is: 1. A high electron mobility transistor (HEMT), comprising: a first binary Group III-nitride barrier layer; a binary Group III-nitride channel layer on the first barrier layer; a second binary Group III-nitride barrier layer on the channel layer, wherein the first barrier l
That which is claimed is: 1. A high electron mobility transistor (HEMT), comprising: a first binary Group III-nitride barrier layer; a binary Group III-nitride channel layer on the first barrier layer; a second binary Group III-nitride barrier layer on the channel layer, wherein the first barrier layer comprises a doped binary Group III-nitride region; and an undoped binary Group III-nitride layer disposed between the doped binary Group III-nitride region and the channel layer. 2. The HEMT of claim 1 wherein the first barrier layer comprises an AIN layer, the channel layer comprises a GaN layer and the second barrier layer comprises an AIN layer. 3. The HEMT of claim 2, wherein the first barrier layer has a thickness of from about 1 nm to about 1 mm, the channel layer has a thickness of from about 0.3 nm to about 10 nm and the second barrier layer has a thickness of from about 0.5 nm to about 50 nm. 4. The HEMT of claim 2, further comprising a GaN layer on the second AIN barrier layer opposite the GaN channel layer. 5. The HEMT of claim 4, wherein the GaN layer on the second AIN barrier layer opposite the GaN channel layer has a thickness of from about 0.3 nm to about 10 nm. 6. The HEMT of claim 4, wherein the GaN layer on the second AIN barrier layer opposite the GaN channel layer is doped or delta doped at an interface between the GaN layer and the second AIN barrier layer. 7. The HEMT of claim 1, wherein the first binary Group III-nitride barrier layer comprises AIN, the binary Group III-nitride channel layer on the first barrier layer comprises InN and the second binary Group III-nitride barrier layer on the channel layer comprises AIN. 8. The HEMT of claim 1, wherein the first binary Group III-nitride barrier layer comprises GaN, the binary Group III-nitride channel layer on the first barrier layer comprises InN and the second binary Group III-nitride barrier layer on the channel layer comprises GaN. 9. The HEMT of claim 1, wherein the first binary Group III-nitride barrier layer comprises GaN, the binary Group III-nitride channel layer on the first barrier layer comprises InN and the second binary Group III-nitride barrier layer on the channel layer comprises AIN. 10. The HEMT of claim 9, wherein GaN, InN and AIN layers are strain balanced. 11. The HEMT of claim 10, further comprising a GaN cap layer on the AIN layer. 12. The HEMT of claim 1, wherein the first binary Group III-nitride barrier layer comprises AIN, the binary Group III-nitride channel layer on the first barrier layer comprises InN and the second binary Group III-nitride barrier layer on the channel layer comprises GaN. 13. The HEMT of claim 1, wherein the HEMT does not include a ternary or quaternary Group III-nitride layer in an active region of the HEMT. 14. A high electron mobility transistor (HEMT), comprising: a first binary Group III-nitride barrier layer; a binary Group III-nitride channel layer on the first barrier layer; and a second binary Group III-nitride barrier layer on the channel layer, wherein the first barrier layer comprises a doped binary Group III-nitride region, wherein the second barrier layer comprises a first doped binary Group III-nitride region on the binary Group III-nitride channel layer opposite the first barrier layer. 15. The HEMT of claim 14, further comprising an undoped binary Group III-nitride layer disposed between the first doped binary Group III-nitride region and the channel layer. 16. A high electron mobility transistor (HEMT). comprising: a first binary Group III-nitride barrier layer; a binary Group III-nitride channel layer on the first barrier layer; a second binary Group III-nitride barrier layer on the channel layer, wherein the second barrier layer comprises a first doped binary Group III-nitride region on the binary Group III-nitride channel layer opposite the first barrier layer; and an undoped binary Group III-nitride layer disposed between the first doped binary Group III-nitride region and the channel layer. 17. A high electron mobility transistor (HEMT), comprising: a first binary Group III-nitride barrier layer; a binary Group III-nitride channel layer on the first barrier layer; a second binary Group III-nitride barrier layer on the channel layer, wherein the first barrier layer comprises an AIN layer, the channel layer comprises a GaN layer and the second barrier layer comprises an AIN layer; and a first doped AIN layer disposed between the first AIN barrier layer and the GaN channel layer. 18. The HEMT of claim 17, wherein the first doped AIN layer comprises a Si doped AIN layer. 19. The HEMT of claim 17, wherein the first doped AIN layer has a thickness of from about 0.2 nm to about 10 nm. 20. The HEMT of claim 17, wherein the first doped AIN layer has a dopant concentration of from about 1×1017 cm-3 to about 1×1021 cm-3. 21. The HEMT of claim 17, further comprising a first undoped AIN layer disposed between the first doped AIN layer and the GaN channel layer. 22. The HEMT of claim 21, wherein the first undoped AIN layer has a thickness of from about 0.3 nm to about 5 nm. 23. The HEMT of claim 17, further comprising a second doped AIN layer disposed between the second AIN barrier layer and the GaN channel layer. 24. The HEMT of claim 23, wherein the second doped AIN layer comprises a Si doped AIN layer. 25. The HEMT of claim 23, wherein the second doped AIN layer has a thickness of from about 0.2 nm to about 10 nm. 26. The HEMT of claim 23, wherein the second doped AIN layer has a dopant concentration of from about 1×1017 cm-3 to about 1×1021 cm-3. 27. The HEMT of claim 23, further comprising a second undoped AIN layer disposed between the second doped AIN layer and the GaN channel layer. 28. The HEMT of claim 27, wherein the second undoped AIN layer has a thickness of from about 0.3 nm to about 5 nm. 29. A high electron mobility transistor (HEMT), comprising: a first binary Group III-nitride barrier layer; a binary Group III-nitride channel layer on the first barrier layer; a second binary Group III-nitride barrier layer on the channel layer, wherein the first barrier layer comprises an AIN layer, the channel layer comprises a GaN layer and the second barrier layer comprises an AIN layer; and a doped AIN layer disposed between the second AIN barrier layer and the GaN channel layer. 30. The HEMT of claim 29, wherein the doped AIN layer comprises a Si doped AIN layer. 31. The HEMT of claim 29, wherein the doped AIN layer has a thickness of from about 0.2 mu to about 10 nm. 32. The HEMT of claim 29, wherein the doped AIN layer has a dopant concentration of from about 1×1017 cm-3 to about 1×1021 cm-3. 33. The HEMT of claim 29, further comprising an undoped AIN layer disposed between the doped AIN layer and the GaN channel layer. 34. The HEMT of claim 33, wherein the undoped AIN layer has a thickness of from about 0.3 nm to about 5 nm.
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