초록 ▼

A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output con

A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangement minimizes color cross talk. An array of microlenses is situated with each microlens covering a plurality of the pixels. The different pixels under each microlens can be aligned along a diagonal. The different pixels under the same microlens can have different integration times, to increase the dynamic range of the imager(s).

대표청구항 ▼

We claim: 1. A CMOS imaging system comprising an array of pixels arranged into rows and columns on an imaging area, the columns being divided into first and second series of columns alternating with one another such that the pixels of the columns of each series are offset by a predetermined amount

We claim: 1. A CMOS imaging system comprising an array of pixels arranged into rows and columns on an imaging area, the columns being divided into first and second series of columns alternating with one another such that the pixels of the columns of each series are offset by a predetermined amount from the pixels of the columns of the other series; an array of microlenses disposed on the imaging area, each microlens covering a plurality of said pixels; each said column having a column amplifier FET having a source electrode and a drain electrode; at least one pair of conductors associated with the first series of columns, with the source and drain electrodes of the column amplifier FETs of the first series of columns being respectively connected thereto; at least one pair of conductors associated with the second series of columns, with the source and drain electrodes of the column amplifier FETs of the second series of columns being respectively connected thereto; first and second output amplifiers each including an additional FET and a feedback path coupled to the respective pair of conductors of the respective series of columns; and image control circuitry coupled to the pixels of said imager; wherein said image control circuitry includes means for applying, for each said plurality of pixels, different integration times to the different respective ones of the plurality of pixels under the same microlens. 2. The system as set forth in claim 1, further comprising lens means for focusing an image of an object onto said CMOS imaging system. 3. The system as set forth in claim 1, wherein said imager control circuitry is operative to provide respective long and short integration times for two of the different pixels under each of said respective microlenses, so as to extend the dynamic range of the CMOS imaging system. 4. A CMOS imaging system comprising an array of pixels arranged into rows and columns on an imaging area, the columns being divided into first and second series of columns alternating with one another such that the pixels of the columns of each series are offset by a predetermined amount from the pixels of the columns of the other series; an array of microlenses disposed on the imaging area, each microlens covering a plurality of said pixels; each said column having a column amplifier FET having a source electrode and a drain electrode; at least one pair of conductors associated with the first series of columns, with the source and drain electrodes of the column amplifier FETs of the first series of columns being respectively connected thereto; at least one pair of conductors associated with the second series of columns, with the source and drain electrodes of the column amplifier FETs of the second series of columns being respectively connected thereto; first and second output amplifiers each including an additional FET and a feedback path coupled to the respective pair of conductors of the respective series of columns; and image control circuitry coupled to the pixels of said imager; and wherein die pixels of each said plurality of pixels are arranged in pairs of pixel regions arranged diagonally on two sides of a pixel control region such that the pairs of pixel regions each extend diagonally defining diagonal zones between successive pairs of pixel regions of that series, wherein the pixels of the other pluralities of pixels are situated within said diagonal zones, and wherein the microlenses are arranged over the pixels within said diagonal zones. 5. The system as set forth in claim 4 wherein said pixel regions are divided into red, blue and green photosensitive areas, such that the red, blue, and green photosensitive areas are aligned diagonally with the corresponding photosensitive areas of the pixel region that is disposed opposite said pixel control regions, and wherein red, blue and green optical filters are disposed as ribbon filters extending diagonally across the respective pixels' photosensitive areas. 6. The system as set forth in claim 4 wherein said pixel regions are divided into respective a group of photosensitive areas, sensitive to a similar plurality of different respective bands of wavelengths. such that the group of photosensitive areas are aligned diagonally with the corresponding group of photosensitive areas of the pixel region that is disposed opposite said pixel control regions, and wherein optical filters are disposed as ribbon filters extending diagonally across the respective pixels' photosensitive areas. 7. A CMOS imaging system comprising an array of pixels arranged into rows and columns on an imagine area, the columns being divided into first and second series of columns alternating with one another such that the pixels of the columns of each series are offset by a predetermined amount from the pixels of the columns of the other series; an array of microlenses disposed on the imagine area, each microlens covering a plurality of said pixels; each said column having a column amplifier FET having a source electrode and a drain electrode; at least one pair of conductors associated with the first series of columns. with the source and drain electrodes of the column amplifier FETs of the first series of columns being respectively connected thereto; at least one pair of conductors associated with the second series of columns, with the source and drain electrodes of the column amplifier FETs of the second series of columns being respectively connected thereto; first and second output amplifiers each including an additional FET and a feedback path coupled to the respective pair of conductors of the respective series of columns; image control circuitry coupled to the pixels of said imager; wherein corresponding pixels of the first and second series of columns are diagonally offset from one another; and wherein the pixels are arranged in pairs of pixel regions arranged diagonally on two sides of a pixel control region such that the pairs of pixel regions each extend diagonally defining diagonal zones between successive pairs of pixel regions of that series, and wherein the pixels of the other series of columns of pixels are situated within said diagonal zones. 8. The CMOS imaging system according to claim 7 wherein said pixel regions are divided into red, blue and green photosensitive areas, such that the red, blue, and green photosensitive areas are aligned diagonally with the corresponding photosensitive areas of the pixel region-that is disposed opposite said pixel control region, and are also aligned with corresponding red, blue, and green photosensitive areas of diagonally aligned pixels of the other series of columns; and wherein red, blue and green optical filters are disposed as ribbon filters extending diagonally across the imaging area. 9. The system as set forth in claim 7, wherein the microlenses are disposed along the diagonals with said ribbon filters. 10. The system as set forth in claim 7, wherein the microlenses are disposed along the diagonals across said ribbon filters. 11. A CMOS imaging system comprising an array of pixels arranged into rows and columns on an imaging area, the columns being divided into first and second series of columns alternating with one another such that the pixels of the columns of each series are offset by a predetermined amount from the pixels of the columns of the other series, and each said pixel having a photosensitive pixel area; an array of microlenses disposed on the imaging area, each microlens covering a plurality of said pixels; each said column having a column amplifier; and image control circuitry coupled to the pixels of said imager: wherein said image control circuitry includes means for applying, for each said plurality of pixels covered by a respective one of said microlenses. different integration times to the different pixels under the same microlens. 12. The system of claim 11, wherein said pixel areas are grouped into regions that are divided into red, blue and green photosensitive areas, such that the red, blue, and green photosensitive areas are aligned with the corresponding photosensitive pixel areas of the pixel region tat is disposed adjacent thereto on a diagonal axis, and wherein red, blue and green optical filters are disposed as ribbon filters extending diagonally across the respective pixels' photosensitive areas; and wherein said image control circuitry is operative to provide different integration times of the red, blue, and green photosensitive areas so as to control color balance of the imaging system. 13. The system of claim 11, wherein said pixel areas are grouped into regions that are divided into respective a plurality of photosensitive areas, sensitive to a similar plurality of different respective bands of wavelengths, such that the plurality of photosensitive areas are aligned with the corresponding photosensitive areas of the pixel region that is disposed adjacent thereto on a diagonal axis, and wherein optical filters are disposed as ribbon filters extending diagonally across the respective pixels' photosensitive areas; and wherein said image control circuitry is operative to provide respective independent integration times of the photosensitive areas that are sensitive to the respective bands of wavelengths, so as to control color balance for the imaging system. 14. A video camera comprising: lens for focusing an image of an object; a photo sensor placed at an image plane of said lens; and output circuitry coupled to said photo sensor for generating a video output signal; wherein said photo sensor includes: an array of pixels arranged into rows and columns on an imaging area, the columns being divided into first and second series of columns alternating with one another such that the pixels of the columns of each series are offset by a predetermined amount from the pixels of the columns of the other series; each said column having a column amplifier FET having a source electrode and a drain electrode; at least one pair of conductors associated with the first series of columns, with the source and drain electrodes of the column amplifier FETs of the first series of columns being respectively connected thereto; at least one pair of conductors associated with the second series of columns, with the source and drain electrodes of the column amplifier FETs of the second series of columns being respectively connected thereto; first and second output amplifiers each including an additional PET and a feedback path coupled to the respective pair of conductors of the respective series of columns; and image control circuitry coupled to the pixels of said imager; wherein corresponding pixels of the first and second series of columns are diagonally offset from one another; wherein the pixels are arranged in pairs of pixel regions arranged diagonally on two sides of a pixel control region such that the pairs of pixel regions each extend diagonally defining diagonal zones between successive pairs of pixel regions of that series; wherein the pixels of the other series of columns of pixels are situated within said diagonal zones; and further comprising an array of microlenses disposed on said imaging area, wherein each of the microlenses thereof is disposed over a plurality of the pixels thereof. 15. The video camera of claim 14, wherein the pixels that are disposed under each of said microlenses are aligned along a diagonal.