IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
UP-0680758
(2007-03-01)
|
등록번호 |
US-7554209
(2009-07-09)
|
우선권정보 |
JP-2004-106224(2004-03-31) |
발명자
/ 주소 |
- Satou, Yukihiro
- Uno, Tomoaki
- Matsuura, Nobuyoshi
- Shiraishi, Masaki
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
4 인용 특허 :
7 |
초록
▼
The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch
The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.
대표청구항
▼
What is claimed is: 1. A semiconductor device including a DC-DC converter, comprising: a first semiconductor chip including a high side MOSFET of the DC-DC converter, the first semiconductor chip having a first gate electrode pad, a first source electrode pad, and a first drain electrode; a second
What is claimed is: 1. A semiconductor device including a DC-DC converter, comprising: a first semiconductor chip including a high side MOSFET of the DC-DC converter, the first semiconductor chip having a first gate electrode pad, a first source electrode pad, and a first drain electrode; a second semiconductor chip including a low side MOSFET of the DC-DC converter, the second semiconductor chip having a second gate electrode pad, a second source electrode pad, and a second drain electrode; a third semiconductor chip including a first driver circuit to drive the high side MOSFET and a second driver circuit to drive the low side MOSFET, the third semiconductor chip having a first electrode pad and a second electrode pad; a resin body covering the first, second, and third semiconductor chips; and a metal plate conductor which is electrically and mechanically connected to the first source electrode pad of the first semiconductor chip, wherein the first electrode pad of the third semiconductor chip is electrically coupled to the first gate electrode pad of the first semiconductor chip, wherein the second electrode pad of the third semiconductor chip is electrically coupled to the second gate electrode pad of the second semiconductor chip, wherein the first source electrode pad of the first semiconductor chip and the second drain electrode of the second semiconductor chip are electrically coupled to each other through the metal plate conductor, wherein a first bonding wire is bonded to the first gate electrode pad of the first semiconductor chip, wherein the first semiconductor chip has a rectangular shape in plan view, with a pair of long sides and a pair of short sides, and wherein the first bonding wire is disposed so as to overlap one of the short sides of the first semiconductor chip. 2. A semiconductor device according to claim 1, further comprising: an input terminal exposed from the resin body and electrically coupled to the first drain electrode of the first semiconductor chip; a ground potential terminal exposed from the resin body and electrically coupled to the second source electrode pad of the second semiconductor chip; and an output terminal exposed from the resin body and electrically coupled to the first source electrode pad of the first semiconductor chip and to the second drain electrode of the second semiconductor chip. 3. A semiconductor device according to claim 2, further comprising: a power supply terminal exposed from the resin body and electrically coupled to one of the first driver circuit and the second driver circuit of the third semiconductor chip. 4. A semiconductor device according to claim 2, wherein the resin body has a top surface and a bottom surface opposite the top surface, and wherein the input terminal, the ground potential terminal, and the output terminal are exposed from the bottom surface of the resin body. 5. A semiconductor device according to claim 4, wherein the input terminal, the ground potential terminal, and the output terminal are positioned such that the respective exposed portions are in a same plane as the bottom surface of the resin body. 6. A semiconductor device according to claim 1, wherein the first bonding wire electrically couples the first electrode pad of the third semiconductor chip to the first gate electrode pad of the first semiconductor chip, wherein the semiconductor device further comprises a second bonding wire electrically coupling the second electrode pad of the third semiconductor chip to the second gate electrode pad of the second semiconductor chip, and wherein a width of the metal plate conductor is greater than respective widths of the first and second bonding wires. 7. A semiconductor device according to claim 6, wherein the third semiconductor chip further has a third electrode pad and a fourth electrode pad, and the semiconductor device further comprises: a third bonding wire electrically coupling the third electrode pad of the third semiconductor chip to the first source electrode pad of the first semiconductor chip; and a fourth bonding wire electrically coupling the fourth electrode pad of the third semiconductor chip to the second source electrode pad of the second semiconductor chip, wherein the width of the metal plate conductor is greater than respective widths of the third and fourth bonding wires. 8. A semiconductor device according to claim 1, wherein the metal plate conductor is disposed so as to overlap one of the long sides of the first semiconductor chip in plan view. 9. A semiconductor device according to claim 8, wherein said one long side of the first semiconductor chip is arranged such that a closest distance between the second semiconductor chip and said one long side is less than a closest distance between the second semiconductor chip and the other long side. 10. A semiconductor device according to claim 8, wherein the first source electrode pad forms a rectangular shape in plan view, with a pair of long sides and a pair of short sides, and wherein the long sides of the first semiconductor chip are parallel to the long sides of the first source electrode pad. 11. A semiconductor device according to claim 1, wherein the metal plate conductor is connected to the first source electrode pad by solder. 12. A semiconductor device according to claim 1, wherein the metal plate conductor is comprised of copper. 13. A semiconductor device according to claim 1, wherein the first bonding wire electrically couples the first electrode pad of the third semiconductor chip to the first gate electrode pad of the first semiconductor chip, wherein the semiconductor device further comprises a second bonding wire electrically coupling the second electrode pad of the third semiconductor chip to the second gate electrode pad of the second semiconductor chip, and wherein the first and second bonding wires are comprised of gold. 14. A semiconductor device according to claim 13, wherein the third semiconductor chip further has a third electrode pad and a fourth electrode pad, and the semiconductor device further comprises: a third bonding wire electrically coupling the third electrode pad of the third semiconductor chip to the first source electrode pad of the first semiconductor chip; and a fourth bonding wire electrically coupling the fourth electrode pad of the third semiconductor chip to the second source electrode pad of the second semiconductor chip, wherein the third and fourth bonding wires are comprises of gold. 15. A semiconductor device according to claim 1, wherein the first gate electrode pad, the first source electrode pad, the second gate electrode pad, and the second source electrode pad are comprised of aluminum. 16. A semiconductor device according to claim 1, wherein the first gate electrode pad and the first source electrode pad are disposed on a top surface of the first semiconductor chip, and the first drain electrode is disposed on a bottom surface of the first semiconductor chip, the top surface being opposite the bottom surface. 17. A semiconductor device according to claim 16, wherein the first and second electrode pads are disposed on a top surface of the third semiconductor chip. 18. A semiconductor device according to claim 17, wherein the third semiconductor chip further has a third electrode pad and a fourth electrode pad, and wherein the third and fourth electrode pads are disposed on the top surface of the third semiconductor chip. 19. A semiconductor device according to claim 1, wherein the first source electrode pad includes a first source electrode pad portion and a second source electrode pad portion, and wherein the metal plate conductor is electrically and mechanically connected to the first source electrode pad portion and to the second source electrode pad portion. 20. A semiconductor device according to claim 19, wherein a first gate electrode wiring of the high side MOSFET, which is electrically connected to the first gate electrode pad, is disposed between the first source electrode pad portion and the second source electrode pad portion. 21. A semiconductor device according to claim 20, wherein the first gate electrode wiring and the first and second source electrode pad portions are formed using a same layer. 22. A semiconductor device according to claim 21, wherein the first gate electrode wiring extends in a direction parallel to the long sides of the first semiconductor chip. 23. A semiconductor device according to claim 1, wherein a second bonding wire is bonded to the second electrode pad of the third semiconductor chip. 24. A semiconductor device according to claim 23, wherein the third semiconductor chip further has a third electrode pad and a fourth electrode pad, wherein a third bonding wire is bonded to the third electrode pad of the third semiconductor chip, and wherein a fourth bonding wire is bonded to the fourth electrode pad of the third semiconductor chip. 25. A semiconductor device according to claim 1, wherein the metal plate conductor does not overlap the first gage electrode pad of the first semiconductor chip in plan view. 26. A semiconductor device according to claim 1, wherein the first bonding wire is bonded to the first electrode pad of the third semiconductor chip, and wherein a second bonding wire is bonded to the second electrode pad of the third semiconductor chip and the second gate electrode pad of the second semiconductor chip. 27. A semiconductor device according to claim 26, wherein a third bonding wire is bonded to the third electrode pad of the third semiconductor chip and the first source electrode pad of the first semiconductor chip, and wherein a fourth bonding wire is bonded to the fourth electrode pad of the third semiconductor chip and the second source electrode pad of the second semiconductor chip. 28. A semiconductor device according to claim 1, wherein the third semiconductor chip further has a third electrode pad and a fourth electrode pad, wherein the third electrode pad of the third semiconductor chip is electrically coupled to the first source electrode pad of the first semiconductor chip, and wherein the fourth electrode pad of the third semiconductor chip is electrically coupled to the second source electrode pad of the second semiconductor chip. 29. A semiconductor device according to claim 1, wherein a second bonding wire is bonded to the first source electrode pad of the first semiconductor chip. 30. A semiconductor device including a DC-DC converter, comprising: a first semiconductor chip including a high side MOSFET of the DC-DC converter, the first semiconductor chip having a first gate electrode pad, a first source electrode pad, and a first drain electrode; a second semiconductor chip including a low side MOSFET of the DC-DC converter, the second semiconductor chip having a second gate electrode pad, a second source electrode pad, and a second drain electrode; a third semiconductor chip including a first driver circuit to drive the high side MOSFET and a second driver circuit to drive the low side MOSFET, the third semiconductor chip having a first electrode pad and a second electrode pad; an input terminal coupled to the first drain electrode of the first semiconductor chip; a ground potential terminal electrically coupled to the second source electrode pad of the second semiconductor chip; an output terminal electrically coupled to the first source electrode pad of the first semiconductor chip and to the second drain electrode of the second semiconductor chip; a first bonding wire, which is comprised of gold, to electrically couple the first electrode pad of the third semiconductor chip to the first gate electrode pad of the first semiconductor chip; a second bonding wire, which is comprised of gold, to electrically couple the second electrode pad of the third semiconductor chip to the second gate electrode pad of the second semiconductor chip; a resin body covering the first, second, and third semiconductor chips, the resin body having a top surface and a bottom surface opposite the top surface; and a metal plate conductor, which is comprised of copper, connected to the first source electrode pad of the first semiconductor chip by solder, wherein the input terminal, the ground potential terminal, and the output terminal are exposed from the bottom surface of the resin body, wherein a width of the metal plate conductor is greater than respective widths of the first and second bonding wires, wherein the first source electrode pad of the first semiconductor chip and the second drain electrode of the second semiconductor chip are coupled together electrically through the metal plate conductor, wherein the first semiconductor chip has a rectangular shape in plan view, with a pair of long sides and a pair of short sides, wherein one of said long sides of the first semiconductor chip is arranged such that a closest distance between the second semiconductor chip and said one long side is less than a closest distance between the second semiconductor chip and the other long side, wherein the metal plate conductor is disposed so as to overlap said one long side in plan view, wherein the first bonding wire is bonded to the first gate electrode pad of the first semiconductor chip, and wherein the first bonding wire is disposed so as to overlap one of the short sides of the first semiconductor chip in plan view. 31. A semiconductor device according to claim 30, further comprising a power supply terminal electrically coupled to one of the first driver circuit and the second driver circuit of the third semiconductor chip. 32. A semiconductor device according to claim 30, wherein the first gate electrode pad, the first source electrode pad, the second gate electrode pad, and the second source electrode pad are comprised of aluminum. 33. A semiconductor device according to claim 30, wherein the first gate electrode pad and the first source electrode pad are disposed on a top surface of the first semiconductor chip, and the drain electrode is disposed on a bottom surface of the first semiconductor chip, the top surface being opposite the bottom surface. 34. A semiconductor device according to claim 30, wherein the first source electrode pad includes a first source electrode pad portion and a second source electrode pad portion, and wherein the metal plate conductor is electrically and mechanically connected to the first source electrode pad portion and to the second source electrode pad portion. 35. A semiconductor device according to claim 34, wherein a first gate electrode wiring of the high side MOSFET, which is electrically connected to the first gate electrode pad, is disposed between the first source electrode pad portion and the second source electrode pad portion. 36. A semiconductor device according to claim 35, wherein the first gate electrode wiring and the first and second source electrode pad portions are formed using a same layer. 37. A semiconductor device according to claim 36, wherein the gate electrode wiring extends in a direction, which is parallel to the long sides of the first semiconductor chip. 38. A semiconductor device according to claim 30, wherein the metal plate conductor does not overlap the first gate electrode pad of the first semiconductor chip in plan view. 39. A semiconductor device according to claim 30, wherein the first source electrode pad forms a rectangular shape in plan view, with a pair of long sides and a pair of short sides, and wherein the long sides of the first semiconductor chip are parallel to the long sides of the first source electrode pad. 40. A semiconductor device according to claim 30, wherein the first bonding wire is bonded to the first electrode pad of the third semiconductor chip and to the first gate electrode pad of the first semiconductor chip, and wherein the second bonding wire is bonded to the second electrode pad of the third semiconductor chip and to the second gate electrode pad of the second semiconductor chip. 41. A semiconductor device according to claim 30, wherein the third semiconductor chip further has a third electrode pad and a fourth electrode pad, and the semiconductor device further comprising: a third bonding wire, which is comprised of gold, to electrically couple the third electrode pad of the third semiconductor chip to the first source electrode pad of the first semiconductor chip; and a fourth bonding wire to electrically couple the fourth electrode pad of the third semiconductor chip to the second source electrode pad of the second semiconductor chip, wherein the width of the metal plate conductor is greater than respective widths of the third and fourth bonding wires, wherein the third bonding wire is bonded to the first source electrode pad of the first semiconductor chip, and wherein the third bonding wire is disposed so as to overlap one of the short sides of the first semiconductor chip in plan view. 42. A semiconductor device according to claim 41, wherein the third bonding wire is bonded to the third electrode pad of the third semiconductor chip and to the first source electrode pad of the first semiconductor chip, and wherein the fourth bonding wire is bonded to the fourth electrode pad of the third semiconductor chip and to the second source electrode pad of the second semiconductor chip.
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