초록 ▼

A duty cycle correcting circuit for an integrated circuit memory automatically corrects the duty cycle of an input clock by measuring the relative difference between the high time and low time of the input signal and using this measurement to achieve a same-frequency, duty cycle adjusted output sign

A duty cycle correcting circuit for an integrated circuit memory automatically corrects the duty cycle of an input clock by measuring the relative difference between the high time and low time of the input signal and using this measurement to achieve a same-frequency, duty cycle adjusted output signal. The duty cycle correcting circuit includes a duty cycle adjust circuit that uses two series-connected N-channel transistors to control the pull-up slew rate of a signal and another N-channel transistor to control the pull-down slew rate of the same signal, two dual-slope integrator circuits, and input and output signal buffering.

대표청구항 ▼

We claim: 1. A duty cycle correcting circuit comprising: a duty cycle adjuster circuit having a clock input, a pull-down bias input, a pull-up bias input, and a compensated output; a first dual-slope integrator having a clock input and a bias output coupled to the pull-up bias input of the duty cyc

We claim: 1. A duty cycle correcting circuit comprising: a duty cycle adjuster circuit having a clock input, a pull-down bias input, a pull-up bias input, and a compensated output; a first dual-slope integrator having a clock input and a bias output coupled to the pull-up bias input of the duty cycle adjuster circuit; a second dual-slope integrator having a clock input and a bias output coupled to the pull-down bias input of the duty cycle adjuster circuit; and an output inverter circuit having an input coupled to the compensated output of the duty cycle adjuster circuit, a first output coupled to the clock input of the first dual-slope integrator circuit, and a second output coupled to the clock input of the second dual-slope integrator circuit and for providing a duty cycle compensated output clock signal, wherein the duty cycle adjust circuit comprises: a first transistor having a gate coupled to the pull-up bias input, and a current path; a second transistor having a gate coupled to the pull-up bias input, and a current path; a third transistor having a gate coupled to the clock input, and a current path; a fourth transistor having a gate coupled to the pull-down bias input, and a current path; a fifth transistor having a gate and drain coupled to the drain of the first transistor, and a current path; a sixth transistor having a gate coupled to the gate of the fifth transistor and the drain of the first transistor, and a current path; and an inverter having an input coupled to the drains of the third and sixth transistors, and an output coupled to the compensated output, wherein the current paths of the first and second transistors are coupled between the drain of the fifth transistor and ground, and the current paths of the third and fourth transistors are coupled between the drain of the sixth transistor and ground. 2. The duty cycle correcting circuit of claim 1 wherein the first, second, third, and fourth transistors each comprise an N-channel transistor. 3. The duty cycle correcting circuit of claim 1 wherein the fifth and sixth transistors each comprise a P-channel transistor. 4. A duty cycle correcting circuit comprising: a duty cycle adjuster circuit having a clock input, a pull-down bias input, a pull-up bias input, and a compensated output; a first dual-slope integrator having a clock input and a bias output coupled to the pull-up bias input of the duty cycle adjuster circuit; a second dual-slope integrator having a clock input and a bias output coupled to the pull-down bias input of the duty cycle adjuster circuit; and an output inverter circuit having an input coupled to the compensated output of the duty cycle adjuster circuit, a first output coupled to the clock input of the first dual-slope integrator circuit, and a second output coupled to the clock input of the second dual-slope integrator circuit and for providing a duty cycle compensated output clock signal, wherein the first dual-slope integrator comprises: a first transistor having a source coupled to a power supply voltage, a gate coupled to the clock input, and a drain; a first resistor coupled between the drain of the first transistor and the bias output; a second transistor having a source coupled to ground, a gate coupled to the clock input, and a drain; a second resistor coupled between the drain of the second transistor and the bias output; and a capacitor coupled between the bias output and ground. 5. The duty cycle correcting circuit of claim 4 wherein the first transistor comprises a P-channel transistor. 6. The duty cycle correcting circuit of claim 4 wherein the second transistor comprises an N-channel transistor. 7. The duty cycle correcting circuit of claim 4 further comprising additional circuitry to allow for duty cycle correction to other than a 50% duty cycle. 8. A duty cycle correcting circuit comprising: a duty cycle adjuster circuit having a clock input, a pull-down bias input, a pull-up bias input, and a compensated output; a first dual-slope integrator having a clock input and a bias output coupled to the pull-up bias input of the duty cycle adjuster circuit; a second dual-slope integrator having a clock input and a bias output coupled to the pull-down bias input of the duty cycle adjuster circuit; and an output inverter circuit having an input coupled to the compensated output of the duty cycle adjuster circuit, a first output coupled to the clock input of the first dual-slope integrator circuit, and a second output coupled to the clock input of the second dual-slope integrator circuit and for providing a duty cycle compensated output clock signal, wherein the second dual-slope integrator comprises: a first transistor having a source coupled to a power supply voltage, a gate coupled to the clock input, and a drain; a first resistor coupled between the drain of the first transistor and the bias output; a second transistor having a source coupled to ground, a gate coupled to the clock input, and a drain; a second resistor coupled between the drain of the second transistor and the bias output; and a capacitor coupled between the bias output and ground. 9. The duty cycle correcting circuit of claim 8 wherein the first transistor comprises a P-channel transistor. 10. The duty cycle correcting circuit of claim 8 wherein the second transistor comprises an N-channel transistor. 11. The duty cycle correcting circuit of claim 8 further comprising additional circuitry to allow for duty cycle correction to other than a 50% duty cycle.