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An ESD protection circuit incorporates an ESD shunt device triggered by an ESD trigger network. In non-powered situations, a first RC time constant in the ESD trigger network, corresponds with the time range of the onset an ESD event and controls application of the ESD shunt device in response to th

An ESD protection circuit incorporates an ESD shunt device triggered by an ESD trigger network. In non-powered situations, a first RC time constant in the ESD trigger network, corresponds with the time range of the onset an ESD event and controls application of the ESD shunt device in response to the ESD event. A second RC time constant in a shunt trigger network is selected to be longer than the first RC time constant and holds-off triggering of a shunt device during ESD shunt protection. When activated during powered-on operation, the shunt device shunts a resistive element in the ESD trigger network forming a third time constant. The shunt device guards against false triggering during noise on a power rail by maintaining the third time constant in the ESD trigger network. The third time constant ensures that power rail voltage buildup due to noise dissipates before a false trigger develops.

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What is claimed is: 1. An ESD protection circuit comprising: an ESD trigger network coupled between a power terminal and ground, the ESD trigger network responsive to an ESD event and further comprising a trigger capacitor coupled to a trigger resistor; at least one logic gate coupled to an output

What is claimed is: 1. An ESD protection circuit comprising: an ESD trigger network coupled between a power terminal and ground, the ESD trigger network responsive to an ESD event and further comprising a trigger capacitor coupled to a trigger resistor; at least one logic gate coupled to an output of the ESD trigger network; an ESD shunt device coupled to an output of the at least one logic gate; a shunt trigger network coupled between the power terminal and ground, the shunt trigger network further comprising a shunt resistor coupled to a shunt capacitor; a shunt device coupled to the output of the ESD trigger network and in parallel with the trigger resistor, a control input of the shunt device coupled to an output of the shunt trigger network; wherein the ESD trigger network is configured to trigger the ESD shunt device, thus shunting the power terminal to ground; and wherein an RC time constant of the ESD trigger network is configured to be significantly reduced by the shunt device shunting the trigger resistor, the shunt device shunting when activated by the circuit having power applied. 2. The circuit of claim 1, wherein the RC time constant of the ESD trigger network is configured to be significantly less than an expected rate of voltage fluctuation on the power terminal due to noise or simultaneous switching outputs produced by an associated device, the ESD trigger network being non-responsive to the noise or simultaneous switching of outputs. 3. The circuit of claim 1, wherein the at least one logic gate is comprised of a latch configured to retain an indication of an ESD event being triggered. 4. The circuit of claim 3, wherein the ESD trigger network is configured to have a nominal RC time constant with the shunt device non-operational, the nominal RC time constant selected to correspond with an expected time range of an onset of the ESD event, the shunt device non-operational with no power applied to the circuit. 5. The circuit of claim 3, wherein a first RC time constant, associated with the ESD trigger network, corresponds with over-voltage characteristics related to an onset of the ESD event during a non-powered condition of the ESD protection circuit, the first RC time constant determined by the trigger capacitor in series with the trigger resistor. 6. The circuit of claim 3, wherein a second RC time constant associated with the shunt trigger network is selected to be longer than an expected period of time corresponding with an onset of the ESD event, the second RC time constant determined by the shunt trigger resistor in series with the shunt trigger capacitor. 7. The circuit of claim 6, wherein the second RC time constant is selected to be about twice as long as an expected period of time corresponding with the onset of the ESD event. 8. The circuit of claim 1, wherein the ESD trigger network is configured to have a nominal RC time constant with the shunt device non-operational, the nominal RC time constant selected to correspond with an expected time range of a duration of the ESD event, the shunt device non-operational with no power applied to the circuit. 9. The circuit of claim 1, wherein a first RC time constant, associated with the ESD trigger network, corresponds with over-voltage characteristics related to a duration of the ESD event during a non-powered condition of the ESD protection circuit, the first RC time constant determined by the trigger capacitor in series with the trigger resistor. 10. The circuit of claim 1, wherein a second RC time constant associated with the shunt trigger network is selected to be longer than an expected period of time corresponding to the ESD event duration, the second RC time constant determined by the shunt trigger resistor in series with the shunt trigger capacitor. 11. The circuit of claim 10, wherein the second RC time constant is selected to be about twice as long as an expected period of time corresponding to the ESD event duration. 12. The circuit of claim 1, wherein the trigger capacitor connects between the power terminal and the trigger resistor, the at least one logic gate comprising an odd number of inverters, the ESD shunt device being a PMOS transistor. 13. The circuit of claim 1, wherein the trigger capacitor connects between the power terminal and the trigger resistor, the at least one logic gate comprising an even number of inverters, the ESD shunt device being a NMOS transistor. 14. The circuit of claim 1, wherein the trigger resistor connects between the power terminal and the trigger capacitor, the at least one logic gate comprising an even number of inverters, the ESD shunt device being a PMOS transistor. 15. The circuit of claim 1, wherein the trigger resistor connects between the power terminal and the trigger capacitor, the at least one logic gate comprising an odd number of inverters, the ESD shunt device being a NMOS transistor. 16. An ESD protection circuit, disposed between a power terminal and a ground terminal, comprising: an ESD trigger means for detecting an ESD event, the ESD trigger means coupled between the power terminal and the ground terminal; at least one logic gate means for triggering an ESD event detection state, the at least one logic gate means coupled to the ESD trigger means; an ESD shunt means for shunting current related to the ESD event, the ESD shunt means coupled to the at least one logic gate means; a shunt means for shunting an element of the ESD trigger means, the shunt means coupled to the ESD trigger means; and a shunt trigger means for triggering the shunt means, the shunt trigger means coupled to the shunt means and coupled between the power terminal and the ground terminal wherein an RC time constant of the ESD trigger means is configured to be reduced by the shunt means shunting the element of the ESD trigger means, the shunt means shunting when activated by the ESD protection circuit having power applied. 17. The ESD protection circuit of claim 16, wherein one of the at least one logic gate means is a latching means for retaining the ESD event detection state. 18. An ESD protection circuit comprising: a first RC network coupled to a power terminal and ground, the first RC network further comprising a first capacitor coupled to a first resistor, the first RC network configured to produce a first RC time constant responsive to an ESD event; at least one logic gate coupled to an output of the first RC network; an ESD shunt device coupled to the logic gate; a second RC network coupled to the power terminal and ground, the second RC network further comprising a second resistor coupled to a second capacitor and configured to produce a second RC time constant longer than the first RC time constant; and a shunt device coupled in parallel with the first resistor, the shunt device coupled to the second RC network; whereby the first RC network is configured to successively trigger the at least one logic gate and the ESD shunt device, the shunt device configured to be triggered to shunt the first resistor after the second RC time constant elapses. 19. The circuit of claim 18, wherein an RC time constant of the ESD protection circuit is configured to be significantly reduced by the shunt device shunting the trigger resistor, the shunt device shunting when activated by the circuit having power applied. 20. The circuit of claim 18, wherein the RC time constant of the ESD protection circuit is configured to be significantly less than an expected rate of voltage fluctuation on the power terminal due to noise or simultaneous switching outputs produced by an associated device, the ESD protection circuit being non-responsive to the noise or simultaneous switching of outputs. 21. The circuit of claim 18, wherein the ESD protection circuit is configured to have a nominal RC time constant with the shunt device non-operational, the nominal RC time constant selected to correspond with an expected time range of a duration of the ESD event, the shunt device non-operational with no power applied to the circuit. 22. The circuit of claim 18, wherein the first RC time constant, associated with the ESD protection circuit, corresponds with over-voltage characteristics related to a duration of the ESD event during a non-powered condition of the ESD protection circuit, the first RC time constant determined by the trigger capacitor in series with the trigger resistor. 23. The circuit of claim 18, wherein the second RC time constant associated with the shunt trigger network is selected to be about twice as long as an expected period of time corresponding with an ESD event duration, the second RC time constant determined by the shunt trigger resistor in series with the shunt trigger capacitor. 24. The ESD protection circuit of claim 18, wherein the logic gate is a latch. 25. The circuit of claim 24, wherein the ESD protection circuit is configured to have a nominal RC time constant with the shunt device non-operational, the nominal RC time constant selected to correspond with an expected time range of an onset of the ESD event, the shunt device non-operational with no power applied to the circuit. 26. The circuit of claim 24, wherein a first RC time constant, associated with the ESD event during a non-powered condition of the ESD protection circuit, the first RC time constant determined by the trigger capacitor in series with the trigger resistor. 27. The circuit of claim 24, wherein a second RC time constant associated with the shunt trigger network is selected to be longer than an expected period of time corresponding with an onset of the ESD event, the second RC time constant determined by the shunt trigger resistor in series with the shunt trigger capacitor. 28. The circuit of claim 18, wherein the trigger capacitor connects between the power terminal and the trigger resistor, the ESD shunt device being a NMOS transistor. 29. The circuit of claim 18, wherein the trigger resistor connects between the power terminal and the trigger capacitor, the ESD shunt device being a PMOS transistor. 30. A method of triggering an ESD protection device disposed between a power terminal and a ground terminal, comprising: ascertaining a first time period related to an expected ESD event; calculating a first RC time constant corresponding to the first time period; selecting a trigger capacitor and a trigger resistor to produce the first RC time constant; sensing an ESD event having an onset timeframe corresponding to the first time period; shunting current produced by the ESD event; ascertaining a second time period longer than the first time period; calculating a second RC time constant corresponding to the second time period; selecting a shunt resistor and a shunt capacitor to produce the second RC time constant; and shunting the trigger resistor when the ESD protection device has power applied. 31. The method of triggering an ESD protection device of claim 30, wherein the second time period is selected to be about twice the first time period. 32. The method of triggering an ESD protection device of claim 30, wherein the first time period corresponds to an onset of the ESD event. 33. The method of triggering an ESD protection device of claim 30, wherein the first time period corresponds to a duration of the ESD event. 34. An ESD protection circuit comprising: an ESD trigger network coupled between a power terminal and ground, the ESD trigger network responsive to an ESD event and further comprising a trigger capacitor coupled to a trigger resistor; at least one logic gate coupled to an output of the ESD trigger network; an ESD shunt device coupled to an output of the at least one logic gate; a shunt trigger network coupled between the power terminal and ground and comprising a shunt resistor coupled to a shunt capacitor; a shunt device coupled to the output of the ESD trigger network and in parallel with the trigger resistor, a control input of the shunt device coupled to an output of the shunt trigger network; wherein the ESD trigger network is configured to trigger the ESD shunt device, thus shunting the power terminal to ground; and wherein the ESD trigger network is configured to have a nominal RC time constant with the shunt device non-operational, the nominal RC time constant selected to correspond with an expected time range of an onset of the ESD event, the shunt device being non-operational with no power applied to the circuit. 35. The circuit of claim 34, wherein the logic gate comprises a latch to retain an indication of a triggered ESD event. 36. The circuit of claim 34, wherein a first RC time constant, associated with the ESD trigger network, corresponds with over-voltage characteristics related to an onset of the ESD event during a non-powered condition of the ESD protection circuit, the first RC time constant determined by the trigger capacitor in series with the trigger resistor. 37. The circuit of claim 36, wherein a second RC time constant associated with the shunt trigger network is selected to be longer than an expected period of time corresponding with an onset of the ESD event, the second RC time constant determined by the shunt trigger resistor in series with the shunt trigger capacitor. 38. An ESD protection circuit comprising: an ESD trigger network coupled between a power terminal and ground, the ESD trigger network responsive to an ESD event and comprising a trigger capacitor coupled to a trigger resistor; at least one logic gate coupled to an output of the ESD trigger network; an ESD shunt device coupled to an output of the at least one logic gate; a shunt trigger network coupled between the power terminal and ground and comprising a shunt resistor coupled to a shunt capacitor; a shunt device coupled to the output of the ESD trigger network and in parallel with the trigger resistor, a control input of the shunt device coupled to an output of the shunt trigger network; wherein the ESD trigger network is configured to trigger the ESD shunt device, thus shunting the power terminal to ground; and wherein an RC time constant associated with the shunt trigger network is selected to be longer than an expected period of time corresponding with an onset of the ESD event, the RC time constant determined by the shunt trigger resistor in series with the shunt trigger capacitor. 39. The circuit of claim 38, wherein the RC time constant is selected to be about twice as long as an expected period of time corresponding with the onset of the ESD event. 40. The circuit of claim 39, wherein the ESD trigger network is configured to have a nominal RC time constant with the shunt device non-operational, the nominal RC time constant selected to correspond with an expected time range of a duration of the ESD event, the shunt device being non-operational with no power applied to the circuit. 41. The circuit of claim 38, wherein the RC time constant corresponds with over-voltage characteristics related to a duration of the ESD event during a non-powered condition of the ESD protection circuit, the RC time constant is set by the trigger capacitor in series with the trigger resistor.