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Dynamic data dependence tracking and its application to branch prediction 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/00
출원번호 UP-0050454 (2005-02-04)
등록번호 US-7571302 (2009-08-24)
발명자 / 주소
  • Chen, Lei
  • Albonesi, David
  • Dropsho, Steve
대리인 / 주소
    Stolowitz Ford Cowger LLP
인용정보 피인용 횟수 : 16  인용 특허 : 9

초록

A data dependence table in RAM relates physical register addresses to instructions such that for each instruction, the registers on whose data the instruction depends are identified. The table is updated for each instruction added to the pipeline. For a branch instruction, the table identifies the r

대표청구항

We claim: 1. A method for dynamically tracking data dependence of a plurality of instructions in a pipeline to be executed by a processor, the method comprising: in a memory which is organized as a plurality of rows and a plurality of columns, each of the plurality of rows corresponding to a regist

이 특허에 인용된 특허 (9)

  1. Asakawa,Takeo, Instruction control device and method therefor.
  2. Sheaffer Gad S.,ILX ; Valentine Robert,ILX, Instruction dependency chain indentifier.
  3. Leung Arthur T., Method for dependency checking using a scoreboard for a pair of register sets having different precisions.
  4. Haitham Akkary ; Kingsum Chow, Processor having multiple program counters and trace buffers outside an execution pipeline.
  5. Martell Robert W. (Hillsboro OR) Hinton Glenn J. (Portland OR) Fetterman Michael A. (Hillsboro OR) Papworth David B. (Beaverton OR) Colwell Robert P. (Portland OR) Glew Andrew F. (Hillsboro OR), Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction.
  6. Ambekar,Asit S.; Nguyen,Dung Q.; Yeung,Raymond C., Register rename array with individual thread bits set upon allocation and cleared upon instruction completion.
  7. Merchant Amit A. ; Sager David J., Scheduling operations using a dependency matrix.
  8. Fetterman Michael A. (Hillsboro OR) Glew Andrew F. (Hillsboro OR) Papworth David B. (Beaverton OR) Hinton Glenn J. (Portland OR) Colwell Robert P. (Portland OR), Speculative and committed resource files in an out-of-order processor.
  9. Uht Augustus K. (44 Torrey Rd. Cumberland RI 02864), System for extracting low level concurrency from serial instruction streams.

이 특허를 인용한 특허 (16)

  1. Bonanno, James J.; Moore, Richard J.; Prasky, Brian R., Branch prediction based on correlating events.
  2. Bonanno, James J.; Moore, Richard J.; Prasky, Brian R., Branch prediction based on correlating events.
  3. Yanoo, Kazuo, Data dependence analyzer, information processor, data dependence analysis method and program.
  4. Mizrahi, Noam; Mandler, Alberto; Koren, Shay; Friedmann, Jonathan, Early termination of segment monitoring in run-time code parallelization.
  5. Gonion, Jeffry E., Enhanced Macroscalar predicate operations.
  6. Gonion, Jeffry E., Enhanced predicate registers having predicates corresponding to element widths.
  7. Brown, Melinda J.; Dieffenderfer, James N.; Morrow, Michael W.; Stempel, Brian M.; McIlvaine, Michael S., Issuing instructions to execution pipelines based on register-associated preferences, and related instruction processing circuits, processor systems, methods, and computer-readable media.
  8. Burky, William E.; Kailas, Krishnan, Method and system for tracking instruction dependency in an out-of-order processor.
  9. Gonion, Jeffry E., Prediction optimizations for Macroscalar vector partitioning loops.
  10. Gonion, Jeffry E., Processing vectors using a wrapping rotate previous instruction in the macroscalar architecture.
  11. Gonion, Jeffry E., Processing vectors using wrapping increment and decrement instructions in the macroscalar architecture.
  12. Gonion, Jeffry E., Processing vectors using wrapping propagate instructions in the macroscalar architecture.
  13. Mizrahi, Noam; Mandler, Alberto; Koren, Shay; Friedmann, Jonathan, Run-time code parallelization with continuous monitoring of repetitive instruction sequences.
  14. Mizrahi, Noam; Mandler, Alberto; Koren, Shay; Friedmann, Jonathan, Run-time parallelization of code execution based on an approximate register-access specification.
  15. Gonion, Jeffry E., Selective suppression of branch prediction in vector partitioning loops until dependency vector is available for predicate generating instruction.
  16. Kultursay, Emre; Ebcioglu, Kemal; Kandemir, Mahmut Taylan, Storage unsharing.
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