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A code is provided which outputs a predetermined code enable signal by executing a simple control, depending on a clock signal frequency, with an optimal circuit scale. A multiplexer receives integers which are relatively prime, and outputs either of them to an adder, depending on comparator output

A code is provided which outputs a predetermined code enable signal by executing a simple control, depending on a clock signal frequency, with an optimal circuit scale. A multiplexer receives integers which are relatively prime, and outputs either of them to an adder, depending on comparator output signal. The adder adds an integer latched by the register and an integer output by the multiplexer, and outputs the result via a multiplexer to the register. The register latches and outputs the received integer to the comparator with a sampling clock signal frequency. In accordance with a threshold set based on the integers and the number of bits of the adder or the register, the comparator outputs a signal having the High state only when the output integer of the register satisfies the threshold condition. The code outputs this as a code enable signal.

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The invention claimed is: 1. A code NCO for generating a code enable signal for code phase observation, comprising: a first multiplexer which is configured to receive two relatively prime integers, and to feed either of the two integers as a first integer output in accordance with a select signal;

The invention claimed is: 1. A code NCO for generating a code enable signal for code phase observation, comprising: a first multiplexer which is configured to receive two relatively prime integers, and to feed either of the two integers as a first integer output in accordance with a select signal; an adder which is configured to add the first integer output from the first multiplexer and an integer output from a register in order to feed a second integer output; a second multiplexer which is configured to receive the second integer output from the adder and a code phase adjustment value, and to feed either of them as a third integer output based on an adjustment signal; the register which is configured to latch and to feed the third integer output from the second multiplexer as a fourth integer output in accordance with a sampling clock signal; and a select signal generator which is configured to output the select signal when the select signal generator detects that the fourth integer output from the register is a predetermined integer value which is previously set, wherein the select signal is the code enable signal and, wherein the select signal generator is a comparator which is configured to compare the fourth integer output from the register with a threshold determined from the two integers in order to output the select signal. 2. A GPS receiver comprising: the code NCO according to claim 1, wherein the GPS receiver captures and tracks a code phase of a GPS signal by using a PN code generated based on a code enable signal output from the code NCO. 3. A code NCO for generating a code enable signal for code phase observation, comprising: a first multiplexer which is configured to receive two relatively prime integers, and to feed either of the two integers as a first integer output in accordance with a select signal; an adder which is to add the first integer from the first multiplexer and an integer output from a register in order to feed a second integer output; a second multiplexer which is configured to receive the second integer output from the adder and a code phase adjustment value, and to feed either of them as a third integer output based on an adjustment signal; the register which is configured to latch and to feed the third integer output from the second multiplexer as a fourth integer output in accordance with a sampling clock signal; and a select signal generator which is configured to output the select signal when the select signal generator detects that the fourth integer output from the register is a predetermined integer value which is previously set, wherein the select signal is the code enable signal and, wherein the select signal generator is an AND operator which is configured to output the select signal by using a result of subjecting values of a plurality of predetermined bits of the register to an AND process. 4. A GPS receiver comprising: the code NCO according to claim 3, wherein the GPS receiver captures and tracks a code phase of a GPS signal by using a PN code generated based on a code enable signal output from the code NCO. 5. A code NCO for generating a code enable signal for code phase observation, comprising: a first multiplexer which is configured to receive two relatively prime integers, and to feed either of the two integers as a first integer output in accordance with a select signal; an adder which is configured to add the first integer output from the first multiplexer and an integer output from a register in order to feed a second integer output; a second multiplexer which is configured to receive the second integer output from the adder and a code phase adjustment value, and to feed either of them as a third integer output based on an adjustment signal; the register which is configured to latch and to feed the third integer output from the second multiplexer as a fourth integer output in accordance with a sampling clock signal; and a select signal generator which is configured to output the select signal when the select signal generator detects that the fourth integer output from the register is a predetermined integer value which is previously set, wherein the select signal is the code enable signal and, wherein the select signal generator is a NOR operator which is configured to output the select signal by using a result of subjecting values of a plurality of predetermined bits of the register to a NOR process. 6. A GPS receiver comprising: the code NCO according to claim 5, wherein the GPS receiver captures and tracks a code phase of a GPS signal by using a PN code generated based on a code enable signal output from the code NCO.