Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-012/00
G06F-009/00
출원번호
UP-0626294
(2007-01-23)
등록번호
US-7577799
(2009-08-31)
발명자
/ 주소
Howard, Ric
Katragadda, Ramana V.
출원인 / 주소
NVIDIA Corporation
대리인 / 주소
Patterson & Sheridan, LLP
인용정보
피인용 횟수 :
4인용 특허 :
49
초록▼
The present invention provides a system and method for implementation and use of a shared memory. The shared memory may be accessed both independently and asynchronously by one or more processes at corresponding nodes, allowing data to be streamed to multiple processes and nodes without regard to sy
The present invention provides a system and method for implementation and use of a shared memory. The shared memory may be accessed both independently and asynchronously by one or more processes at corresponding nodes, allowing data to be streamed to multiple processes and nodes without regard to synchronization of the plurality of processes. The various nodes may be adaptive computing nodes, kernel or controller nodes, or one or more host processor nodes. The present invention maintains memory integrity, not allowing memory overruns, underruns, or deadlocks. The present invention also provides for "push back" after a memory read, for applications in which it is desirable to "unread" some elements previously read from the memory.
대표청구항▼
The invention claimed is: 1. A method of controlling independent and asynchronous access to a memory by a plurality of processes, the method comprising: while providing for independent and asynchronous performance of a memory read process of the plurality of processes, independently and asynchronou
The invention claimed is: 1. A method of controlling independent and asynchronous access to a memory by a plurality of processes, the method comprising: while providing for independent and asynchronous performance of a memory read process of the plurality of processes, independently and asynchronously performing a memory write process of the plurality of processes, wherein the memory write process comprises: copying a memory full indicator to produce a first copy of the memory full indicator; copying a read index that is updated by the memory read process, the read index copy indicating a read element position in the memory; when the first copy of the memory full indicator indicates that the memory is not full, determining an available write count from the read index copy and a write index, the write index indicating a write element position in the memory; beginning at the write element position, writing an amount of data corresponding to the available write count; updating the write index to indicate a next write element position based upon the amount of data written; and subsequent to copying the read index and determining the available write count, but prior to writing the amount of data corresponding to the available write count, changing the read index to have a different value than the read index copy and clearing the memory full indicator to indicate that the memory is not full by the memory read process. 2. The method of claim 1, further comprising: determining whether the updated write index is equal to the read index copy. 3. The method of claim 2, further comprising: when the updated write index is equal to the read index copy, setting the memory full indicator to indicate that the memory is full or may be full. 4. The method of claim 1, wherein the amount of data corresponding to the available write count is an amount of data which is less than or equal to the available write count. 5. The method of claim 1, wherein the memory read process comprises: copying the memory full indicator to produce a second copy of the memory full indicator; copying the write index to produce a write index copy; determining an available read count from the read index and the write index copy; beginning at the read element position, reading an amount of data corresponding to the available read count; and updating the read index to indicate a next read element position based on the amount of data read. 6. The method of claim 5, further comprising: subsequent to updating the read index, when the second copy of the memory full indicator indicates that the memory is full or may be full, clearing the memory full indicator to indicate that the memory is not full. 7. The method of claim 5, further comprising: prior to determining the available read count, when the second copy of the memory full indicator indicates that the memory is full or may be full, and when the write index copy is not equal to the read index, clearing the memory full indicator to indicate that the memory is not full. 8. The method of claim 1, wherein the memory read process further comprises: copying the memory full indicator to produce a second copy of the memory full indicator; copying the write index to produce a write index copy; determining an available read count from the read index and the write index copy; beginning at the read element position, reading a plurality of data elements corresponding to the available write count; selecting a subset of data elements from the plurality of data elements for a subsequent read process; determining an element position corresponding to an initial data element of the subset of data elements in the memory, as a next read element position and as a next write element position; commencing at the next write element position, writing the subset of data elements to the memory; and updating the read index to indicate the next read element position for the subsequent read process. 9. The method of claim 8, wherein the writing of the subset of data elements to the memory is performed without modification of the write index. 10. A system for controlling independent and asynchronous access to a memory by a plurality of processes, the system comprising: a memory; a second node coupled to the memory, the second node capable of independently and asynchronously performing a memory write process, of the plurality of processes, by copying a memory full indicator to produce a first copy of the memory full indicator and copying a read index to produce a read index copy indicating a read element position in the memory; when the first copy of the memory full indicator indicates that the memory is not full, the second node further capable of determining an available write count from the read index copy and a write index, the write index indicating a write element position in the memory; beginning at the write element position, the second node further capable of writing an amount of data corresponding to the available write count and updating the write index to indicate a next write element position based upon the amount of data written; and a first node coupled to the memory, the first node capable of independently and asynchronously performing a memory read process, wherein subsequent to the first node copying the read index and determining the available write count, but prior to the first node writing the amount of data corresponding to the available write count, the first node changes the read index to have a different value than the read index copy and clears the memory full indicator to indicate that the memory is not full. 11. The system of claim 10, wherein the second node is further capable of determining whether the updated write index is equal to the read index copy. 12. The system of claim 11, wherein when the updated write index is equal to the read index copy, the second node is further capable of setting the memory full indicator to indicate that the memory is full or may be full. 13. The system of claim 10, wherein the first node is further capable of copying the memory full indicator to produce a second copy of the memory full indicator and copying the write index to produce a write index copy; determining an available read count from the read index and the write index copy; beginning at the read element position, reading an amount of data corresponding to the available read count; and wherein the first node is further capable of updating the read index to indicate a next read element position based on the amount of data read. 14. The system of claim 13, wherein subsequent to updating the read index, when the second copy of the memory full indicator indicates that the memory is full or may be full, the first node is further capable of clearing the memory full indicator to indicate that the memory is not full. 15. The system of claim 13, wherein prior to determining the available read count, when the second copy of the memory full indicator indicates that the memory is full or may be full, and when the write index copy is not equal to the read index, the first node is further capable of clearing the memory full indicator to indicate that the memory is not full. 16. The system of claim 13, wherein the amount of data corresponding to the available read count is an amount of data which is less than or equal to the available read count. 17. The system of claim 10, wherein the first node is capable of copying the memory full indicator to produce a second copy of the memory full indicator and copying the write index to produce a write index copy; determining an available read count from the read index and the write index copy; beginning at the read element position, reading a plurality of data elements corresponding to the available write count; selecting a subset of data elements from the plurality of data elements for a subsequent read process; wherein the first node is further capable of determining an element position corresponding to an initial data element of the subset of data elements in the memory, as a next read element position and as a next write element position; commencing at the next write element position, writing the subset of data elements to the memory; and updating the read index to indicate the next read element position for the subsequent read process. 18. The system of claim 17, wherein the first node is further capable of writing the subset of data elements to the memory without modification of the write index. 19. The method of claim 1, wherein the memory read process further comprises determining that data elements are required for a subsequent read process and updating the read index to indicate the next read element position for the subsequent read process. 20. The system of claim 1, wherein the first node is further capable of determining that data elements are required for a subsequent read process and updating the read index to indicate the next read element position for the subsequent read process.
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