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Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-012/00
  • G06F-009/00
출원번호 UP-0626294 (2007-01-23)
등록번호 US-7577799 (2009-08-31)
발명자 / 주소
  • Howard, Ric
  • Katragadda, Ramana V.
출원인 / 주소
  • NVIDIA Corporation
대리인 / 주소
    Patterson & Sheridan, LLP
인용정보 피인용 횟수 : 4  인용 특허 : 49

초록

The present invention provides a system and method for implementation and use of a shared memory. The shared memory may be accessed both independently and asynchronously by one or more processes at corresponding nodes, allowing data to be streamed to multiple processes and nodes without regard to sy

대표청구항

The invention claimed is: 1. A method of controlling independent and asynchronous access to a memory by a plurality of processes, the method comprising: while providing for independent and asynchronous performance of a memory read process of the plurality of processes, independently and asynchronou

이 특허에 인용된 특허 (49)

  1. Sturges, Andrew Craig; May, David, Cache system.
  2. Popli Sanjay (Sunnyvale CA) Pickett Scott (Los Gatos CA) Hawley David (Belmont CA) Moni Shankar (Santa Clara CA) Camarota Rafael C. (San Jose CA), Configuration features in a configurable logic array.
  3. Bernard J. New, Dedicated function fabric for use in field programmable gate arrays.
  4. L'Ecuyer Brian Peter, Determining thresholds and wrap-around conditions in a first-in-first-out memory supporting a variety of read and write transaction sizes.
  5. Langhammer, Martin; Starr, Gregory; Hwang, Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.
  6. Carlson, Jeff M.; Callison, Ryan A., Disconnecting a device on a cache line boundary in response to a write command.
  7. Eccles Edward S. (Bishop\s Cleeve GB2), Electronic circuit assembly an a substrate containing programmable switches.
  8. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., FPGA configurable logic block with multi-purpose logic/memory circuit.
  9. Trimberger Stephen M., Field programmable gate array having programming instructions in the configuration bitstream.
  10. Law Edwin S. ; Buch Kiran B. ; Baxter Glenn A. ; Pang Raymond C., Hardwire logic device emulating an FPGA.
  11. Stephen L. Wasson, Heterogeneous programmable gate array.
  12. Tavana Danesh ; Yee Wilson K. ; Trimberger Stephen M., Integrated circuit with field programmable and application specific logic areas.
  13. Cooke Laurence H. ; Phillips Christopher E. ; Wong Dale, Integrated processor and programmable data path chip for reconfigurable computing.
  14. Wong Dale ; Phillips Christopher E. ; Cooke Laurence H., Integrated processor and programmable data path chip for reconfigurable computing.
  15. DeHon Andre ; Mirsky Ethan ; Knight ; Jr. Thomas F., Intermediate-grain reconfigurable processing device.
  16. DeHon Andre ; Mirsky Ethan ; Knight ; Jr. Thomas F., Intermediate-grain reconfigurable processing device.
  17. Master Paul L. ; Hatley William T. ; Scheuermann II Walter J. ; Goodman Margaret J., Method and apparatus for adaptable digital protocol processing.
  18. Cummings Mark R., Method and apparatus for communicating information.
  19. Coverston Harriet G. (New Brighton MN) Crouse Donald D. (Murphy TX), Method and apparatus for file storage allocation for secondary storage using large and small file blocks.
  20. Bhargava Gautam ; Desai Paramesh Sampatrai ; Goel Piyush ; Hoa Peter ; Lin Fen-Ling ; Iyer Balakrishna Raghavendra ; Mukai Jerry ; Perlman William Samuel ; Tie Hong Sang, Method and apparatus for generating dynamic and hybrid sparse indices for workfiles used in SQL queries.
  21. Reiter Allen (Haifa ILX), Method and computer system for implementing concurrent accesses of a database record by multiple users.
  22. Bertolet Allan Robert ; Clinton Kim P.N. ; Gould Scott Whitney ; Keyser III Frank Ray ; Reny Timothy Shawn ; Zittritsch Terrance John, Method and system for layout and schematic generation for heterogeneous arrays.
  23. Cooke Laurence H. ; Phillips Christopher E. ; Wong Dale, Method for compiling high level programming languages into an integrated processor with reconfigurable logic.
  24. Mohan Sundararajarao ; Trimberger Stephen M., Method for configuring FPGA memory planes for virtual hardware computation.
  25. Harrison David A. ; Silver Joshua M. ; Soe Soren T., Method for programming complex PLD having more than one function block type.
  26. Lee Peter ; Carpenter Brian Ashley ; Noll Mark Garner ; Reiland Robert E., Mobile client computer with radio frequency transceiver.
  27. Loen Larry Wayne, Multiprocessor scaleable system and method for allocating memory from a heap.
  28. Camarota Rafael C. (San Jose CA) Furtek Frederick C. (Menlo Park CA) Ho Walford W. (Saratoga CA) Browder Edward H. (Saratoga CA), Programmable logic cell and array.
  29. Camarota Rafael C. (San Jose CA) Furtek Frederick C. (Menlo Park CA) Ho Walford W. (Saratoga CA) Browder Edward H. (Saratoga CA), Programmable logic cell and array with bus repeaters.
  30. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.
  31. Langhammer, Martin; Hwang, Chiao Kai; Starr, Gregory, Programmable logic device including multipliers and configurations thereof to reduce resource utilization.
  32. Katsutoshi Ito JP, Radio communication apparatus employing a rake receiver.
  33. Ebeling William Henry Carl ; Cronquist Darren Charles ; Franklin Paul David, Reconfigurable computing architecture for providing pipelined data paths.
  34. Alan David Marshall GB; Anthony Stansfield GB; Jean Vuillemin FR, Reconfigurable processor devices.
  35. Trimberger Stephen M., Reprogrammable instruction set accelerator.
  36. Kelleher Brian M. ; Dewey Thomas E., Scalable graphics processor architecture.
  37. Macias Nicholas J. ; Henry ; III Lawrence B. ; Raju Murali Dandu, Self-reconfigurable parallel processor made from regularly-connected self-dual code/data processing cells.
  38. Kopp Randall L. (Irvine CA) Johnson S. Val (Anaheim CA), Single-chip self-configurable parallel processor.
  39. Okada, Yoshiyuki; Tokuyo, Masanaga; Yoshida, Shigeru; Shimoi, Hiroyuki; Okayasu, Naoaki, Storage control apparatus and method for compressing data for disk storage.
  40. Baxter Michael A., System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware.
  41. Iadanza Joseph Andrew (Hinesburg VT), System and method for dynamically reconfiguring a programmable gate array.
  42. Davis Donald J. ; Bennett Toby D. ; Harris Jonathan C. ; Miller Ian D. ; Edwards Stephen G., System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects.
  43. Flax Stephen W. (Wauwatosa WI) Bahr Dennis E. (Middleton WI), System for the compacting and logical linking of data blocks in files to optimize available physical storage.
  44. Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert Anders (San Jose CA) Wong Jennifer (Fremont CA), Time multiplexed programmable logic device.
  45. Wise Adrian Philip,GBX, Tokens-based adaptive video processing arrangement.
  46. Wheeler James E. (Schenectady NY) Hardy Robert M. (Scotia NY) Dunki-Jacobs Robert J. (Saratoga NY) Premerlani William J. (Scotia NY), VLSI programmable digital signal processor.
  47. Furtek Frederick C. (Menlo Park CA) Camarota Rafael C. (San Jose CA), Versatile programmable logic cell for use in configurable logic arrays.
  48. Agrawal Prathima ; Cravatts Mark Robert ; Trotter John Andrew ; Srivastava Mani Bhushan, Wireless adapter architecture for mobile computing.
  49. Athanas Peter ; Bittner ; Jr. Ray A., Worm-hole run-time reconfigurable processor field programmable gate array (FPGA).

이 특허를 인용한 특허 (4)

  1. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  2. Kim, Jinwoo; Kim, Seong Yeon; Park, Jaegeun; Shin, Hyo-Deok; Lee, Younggeun; Cho, Youngjin, Nonvolatile memory device and program method thereof.
  3. Riley, John Reed; Wortendyke, David A.; Marucheck, Michael J., Using distributed queues in an overlay network.
  4. Addison, Edward A.; DeVal, Peggy A.; Lee, Philip R.; Wright, Andrew, Validating run-time references.
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