[특허]Multiple chip package module including die stacked over encapsulated package

[미국특허] Multiple chip package module including die stacked over encapsulated package 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-023/02
출원번호	UP-0381901 (2006-05-05)
등록번호	US-7582960 (2009-09-16)
발명자 / 주소	Karnezos, Marcos
출원인 / 주소	STATS ChipPAC Ltd.
인용정보	피인용 횟수 : 6 인용 특허 : 112

초록

A module having multiple die includes a first package (such as a land grid array package) inverted and mounted upon a lower substrate, and one or more die mounted or stacked over the upward-facing side of the inverted package.

대표청구항 ▼

What is claimed is: 1. A multiple chip package module comprising: a module having a substrate and a package encapsulant on the substrate; a first package comprising: a first package substrate having a die mount side and a land side, a first package die mounted on the die mount side of the first package substrate, a first encapsulant covering the first package die and the die mount side of the first package substrate, and the first package being inverted and supported by the first encapsulant on the package encapsulant over a first side of the module substrate; wire bonds connecting a land side of the first package substrate with the first side of the module substrate; and a module encapsulant covering the land side. 2. The multiple chip package module of claim 1, further comprising a second additional die mounted over the module substrate and supporting the first encapsulant over the module substrate. 3. The multiple chip package module of claim 1 further comprising: a second additional die mounted over the module substrate; and wire bonds electrically connecting the second additional die with the module substrate. 4. The multiple chip package module of claim 1 further comprising: a second additional die mounted over the module substrate; wire bonds electrically connecting the second additional die with the module substrate; a second encapsulant encapsulating the second additional die; and the module encapsulant around the first encapsulant and package encapsulant over the module substrate. 5. The multiple chip package module of claim 1 wherein the first package comprises a plurality of die stacked over the die mount side of the first package substrate. 6. The multiple chip package module of claim 1 wherein the first package further comprises a second package die stacked over the first package die. 7. The multiple chip package module of claim 1 further comprising: a second additional die mounted over the module substrate; wire bonds electrically connecting the second additional die with the module substrate; second encapsulant encapsulating the second additional die, the second encapsulant supporting the first encapsulant over the module substrate; and a third encapsulant encapsulating the first and second encapsulants. 8. The multiple chip package module of claim 1 further comprising: a second additional die mounted on the land side of the first package substrate and electrically connected with the first package substrate. 9. The multiple chip package module of claim 1 further comprising a second additional die mounted on the land side of the first package substrate; wire bonds electrically connecting the second additional die with the land side of the first package substrate; and a second encapsulant encapsulating the first encapsulant and the second additional die. 10. The multiple chip package module of claim 1 wherein a plurality of die are mounted on the land side of the first package substrate and are electrically connected with the land side of the package substrate by wire bonding. 11. The multiple chip package module of claim 1 wherein the first encapsulant is mounted on the module substrate. 12. A computer containing the multiple chip package module of claim 1. 13. A portable electronic apparatus containing the multiple chip package module of claim 1. 14. A mobile telecommunications device containing the multiple chip package module of claim 1.

이 특허에 인용된 특허 (112) 인용/피인용 타임라인 분석

Makoto Terui JP, BGA package and method for fabricating the same.
상세보기
Fee, Setho Sing; Chye, Lim Thiam; Heppler, Steven W.; Yin, Leng Nam; Tan, Keith; Guay, Patrick; Tian, Edmund Lua Koon; Eng, Yap Kah; Seng, Eric Tan Swee, Ball grid array interposer, packages and methods.
상세보기
Kaul Sunil (Fremont CA) Laird Douglas A. (Los Gatos CA), Ball grid array packages for high speed applications.
상세보기
Koopmans, Michel, Bumping technology in stacked die configurations.
상세보기
Culnane Thomas Moran ; Gaynes Michael Anthony ; Seto Ping Kwong ; Shaukatullah Hussain, Chip carrier modules with heat sinks attached by flexible-epoxy.
상세보기
Akram, Salman, Chip package with grease heat sink.
상세보기
Shyue Fong Quek MY; Ying Keung Leung SG; Sang Yee Loong SG; Ting Cheong Ang SG, Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection.
상세보기
Heim Craig G. ; Hooker Wade Leslie ; Trivedi Ajit Kumar, Cooling structure for electronic components.
상세보기
Wu, Chi-Chuan; Huang, Chien-Ping, Crack-preventive semiconductor package.
상세보기
Barrow Michael, Custom corner attach heat sink design for a plastic ball grid array integrated circuit package.
상세보기
Choi, Ill Heung, Duel die package.
상세보기
Akiba,Masayuki; Ichikawa,Kinya; Kubota,Jiro; Kumamoto,Takashi, Encapsulation of a stack of semiconductor dice.
상세보기
Combs, Edward G.; Sheppard, Robert P.; Pun, Tai Wai; Ng, Hau Wan; Fan, Chun Ho; McLellen, Neil Robert, Enhanced thermal dissipation integrated circuit package.
상세보기
Moden Walter L., Flip chip adaptor package for bare die.
상세보기
Moden, Walter L., Flip chip adaptor package for bare die.
상세보기
Moden, Walter L., Flip chip adaptor package for bare die.
상세보기
Song, Young-Jae; Kwon, Young-Shin; Youm, Kun-Dae; Kim, Young-Soo, Higher-density memory card.
상세보기
Bertin Claude Louis ; Ference Thomas George ; Howell Wayne John ; Sprogis Edmund Juris, Highly integrated chip-on-chip packaging.
상세보기
Hisashi Takeda JP, Interposer for separating stacked semiconductor chips mounted on a multi-layer printed circuit board.
상세보기
Maeda, Takehiko; Tsukano, Jun, Light thin stacked package semiconductor device and process for fabrication thereof.
상세보기
Anthony J. LoBianco ; Frank J. Juskey ; Stephen G. Shermer ; Vincent DiCaprio ; Thomas P. Glenn, Making semiconductor packages with stacked dies and reinforced wire bonds.
상세보기
Lee Shaw Wei (San Jose CA), Maximized substrate design for grid array based assemblies.
상세보기
Nguyen Luu ; Prabhu Ashok ; Kelkar Nikhil ; Takiar Hem P., Method and apparatus for forming a plastic chip on chip package module.
상세보기
Akram Salman ; Brooks Jerry M., Method of constructing stacked packages.
상세보기
Koopmans, Michel, Method of fabricating stacked die configurations utilizing redistribution bond pads.
상세보기
Glenn, Thomas P.; Smith, Lee J.; Zoba, David A.; Ramakrishna, Kambhampati; DiCaprio, Vincent, Method of making a semiconductor package including stacked semiconductor dies.
상세보기
Tomihara, Seiichi, Method of manufacturing a semiconductor device having flexible wiring substrate.
상세보기
Kakimoto Noriko,JPX ; Suematsu Eiji,JPX, Millimeter wave semiconductor device.
상세보기
Pu, Han-Ping; Huang, Chih-Ming; Huang, Chien-Ping, Module device of stacked semiconductor packages and method for fabricating the same.
상세보기
Michael B. Ball, Multi-chip device utilizing a flip chip and wire bond assembly.
상세보기
Ming-Hsun Lee TW; Chin-Te Chen TW, Multi-chip module.
상세보기
Vaiyapuri Venkateshwaran,SGX ; Yang Jicheng,SGX, Multi-chip module with stacked dice.
상세보기
Liu,Cheng Cheng, Multi-chip package combining wire-bonding and flip-chip configuration.
상세보기
Kao-Yu Hsu TW; Su Tao TW, Multichip module.
상세보기
Fogal Rich (Boise ID) Ball Michael B. (Boise ID), Multichip module having a stacked chip arrangement.
상세보기
Michii, Kazunari; Akiyama, Tatsuhiko, Multiple chip package semiconductor device.
상세보기
Lo, Randy H. Y.; Huang, Chien-Ping; Wu, Chi-Chuan, Multiple stacked-chip packaging structure.
상세보기
Jeansonne Jeff K., Opposed ball grid array mounting.
상세보기
Shim, Il Kwon; Chow, Seng Guan; Balanon, Gerry, PBGA substrate for anchoring heat sink.
상세보기
Junichi Asada JP, Package having very thin semiconductor chip, multichip module assembled by the package, and method for manufacturing the same.
상세보기
Chen, Jian-Cheng; Hsiao, Wei-Min, Package of a chip with beveled edges.
상세보기
Chye, Lim Thiam; Fee, Setho Sing; Seng, Eric Tan Swee, Packaged microelectronic component assemblies.
상세보기
Hsu, Chi-Hsing, Quad flat no-lead chip carrier.
상세보기
Uchida, Yasufumi; Saeki, Yoshihiro, Rearrangement sheet, semiconductor device and method of manufacturing thereof.
상세보기
Belgacem Haba ; Donald V. Perino ; Sayeh Khalili, Redistributed bond pads in stacked integrated circuit die package.
상세보기
Ichinose, Michihiko; Takizawa, Tomoko; Honda, Hirokazu; Kata, Keiichirou, Resin-encapsulated semiconductor device.
상세보기
Kondo, Takashi; Bando, Koji; Shibata, Jun; Narutaki, Kazuko, Resin-sealed chip stack type semiconductor device.
상세보기
Hideki Ishii JP; Kazunari Michii JP; Jun Shibata JP; Moriyoshi Nakashima JP, Semiconductor device.
상세보기
Ichikawa, Sunji, Semiconductor device.
상세보기
Ozawa Kaname,JPX ; Okuda Hayato,JPX ; Hiraoka Tetsuya,JPX ; Sato Mitsutaka,JPX ; Akashi Yuji,JPX ; Okada Akira,JPX ; Harayama Masahiko,JPX, Semiconductor device.
상세보기
Tadashi Komiyama JP, Semiconductor device.
상세보기
Terui, Makoto, Semiconductor device.
상세보기
Kurita, Yoichiro; Shironouchi, Toshiaki; Tetsuka, Takashi, Semiconductor device and method for manufacturing the same.
상세보기
Ohuchi Shinji,JPX ; Yamada Shigeru,JPX ; Shiraishi Yasushi,JPX, Semiconductor device and method for manufacturing the same.
상세보기
Nakayama, Hirohisa; Taniguchi, Jun; Abe, Takashi; Nakayama, Toshinori, Semiconductor device and method of fabricating the same, circuit board, and electronic equipment.
상세보기
Emoto, Yoshiaki, Semiconductor device and method of making the same, circuit board and electronic equipment.
상세보기
Ichinose, Michihiko, Semiconductor device and packaging method thereof.
상세보기
Jiang, Tongbi; Fee, Setho Sing; Yean, Tay Wuu; Chye, Lim Thiam, Semiconductor device assemblies and packages including multiple semiconductor devices and methods.
상세보기
Fumihiko Taniguchi JP; Akira Takashima JP, Semiconductor device having an interconnecting post formed on an interposer within a sealing resin.
상세보기
Fukui, Yasuki; Narai, Atsuya, Semiconductor device having insulation layer and adhesion layer between chip lamination.
상세보기
Uchida, Yasufumi, Semiconductor device having multi-chip package.
상세보기
Tamaki Kazuo,JPX ; Saza Yasuyuki,JPX ; Dotta Yoshihisa,JPX, Semiconductor device using a chip scale package.
상세보기
Mori Ryuichiro,JPX, Semiconductor module comprising semiconductor packages.
상세보기
Karnezos,Marcos; Carson,Flynn, Semiconductor multi-package module having inverted bump chip carrier second package.
상세보기
Karnezos,Marcos, Semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package.
상세보기
Karnezos,Marcos, Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package.
상세보기
Karnezos, Marcos, Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package.
상세보기
Karnezos,Marcos, Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package.
상세보기
Karnezos,Marcos, Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package.
상세보기
Karnezos,Marcos, Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages.
상세보기
Karnezos,Marcos, Semiconductor multi-package module having wire bond interconnect between stacked packages.
상세보기
Karnezos, Marcos, Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield.
상세보기
Karnezos, Marcos, Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages.
상세보기
Karnezos,Marcos, Semiconductor multipackage module including processor and memory package assemblies.
상세보기
Liao, Chih-Chin; Pu, Han-PIng; Huang, Chien-Ping, Semiconductor package.
상세보기
Tzu Chung-Hsing,TWX, Semiconductor package having multi-dies.
상세보기
Huang, Chien-Ping, Semiconductor package with flash-proof device.
상세보기
Akram, Salman; Brooks, Jerry M., Semiconductor package with stacked substrates and multiple semiconductor dice.
상세보기
Karnezos,Marcos, Semiconductor stacked multi-package module having inverted second package.
상세보기
Karnezos, Marcos, Semiconductor stacked multi-package module having inverted second package and electrically shielded first package.
상세보기
Karnezos,Marcos; Shim,Il Kwon; Han,Byung Joon; Ramakrishna,Kambhampati; Chow,Seng Guan, Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides.
상세보기
Lin Paul T. (Austin TX), Shielded liquid encapsulated semiconductor device and method for making the same.
상세보기
Takahashi Nobuaki,JPX ; Kyougoku Yoshitaka,JPX ; Hashimoto Katsumasa,JPX ; Miyazaki Shinichi,JPX, Shock resistant semiconductor device and method for producing same.
상세보기
De Givry Jacques (Les Loges En Josas FRX), Solid state memory modules and memory devices including such modules.
상세보기
Yang,Chaur Chin; Wang,Hsueh Te, Stack type flip-chip package.
상세보기
Warren M. Farnworth ; Alan G. Wood ; Mike Brooks, Stackable semiconductor package having conductive layer and insulating layers and method of fabrication.
상세보기
Tao Su,TWX ; Lo Kuang-Lin,TWX ; Chou Kuang-Chun,TWX ; Chen Shih-Chih,TWX, Stacked chip assembly utilizing a lead frame.
상세보기
McMahon, John F., Stacked chip packaging.
상세보기
Akram Salman, Stacked leads-over chip multi-chip module.
상세보기
Mess, Leonard E.; Brooks, Jerry M.; Corisis, David J., Stacked mass storage flash memory package.
상세보기
Corisis, David J., Stacked microelectronic dies and methods for stacking microelectronic dies.
상세보기
Degani, Yinon; Dudderar, Thomas Dixon; Sun, Liguo; Zhao, Meng, Stacked module package.
상세보기
Takiar Hem P. (Fremont CA) Lin Peng-Cheng (Cupertino CA), Stacked multi-chip modules and method of manufacturing.
상세보기
Kikuma, Katsuhito; Ikeda, Mitsutaka; Tsukidate, Yoshihiro; Akashi, Yuji; Ozawa, Kaname; Takashima, Akira; Nishimura, Takao, Stacked semiconductor device and method of producing the same.
상세보기
Kikuma, Katsuhito; Ikeda, Mitsutaka; Tsukidate, Yoshihiro; Akashi, Yuji; Ozawa, Kaname; Takashima, Akira; Uno, Tadashi; Nishimura, Takao; Ando, Fumihiko; Onodera, Hiroshi; Okuda, Hayato, Stacked semiconductor device and method of producing the same.
상세보기
St. Amand, Roger D.; Perelman, Vladimir, Stacked semiconductor die assembly having at least one support.
상세보기
Baek, Joong-hyun; Lee, Jin-yang; Im, Yun-hyeok; Lee, Tae-koo, Stacked semiconductor module and method of manufacturing the same.
상세보기
Pedron, Jr., Serafin P., Stacked semiconductor package and method of manufacturing the same.
상세보기
Jichen Wu TW; Meng Ru Tsai TW; Nai Hua Yeh TW; Chen Pin Peng TW, Stacked structure of semiconductor means and method for manufacturing the same.
상세보기
St. Amand,Roger D.; Kim,InTae; Perelman,Vladimir, Stacked-die extension support structure and method thereof.
상세보기
Pu, Han-Ping; Lo, Randy H. Y.; Her, Tzong-Dar; Huang, Chien-Ping; Hsiao, Cheng-Shiu; Wu, Chi-Chuan, Stacked-die package structure.
상세보기
Wen Chuan Chen TW; Kuo Feng Peng TW; Jichen Wu TW; Chia Jung Chang TW, Structure of stacked integrated circuits.
상세보기
Hoffman, Paul Robert; Zoba, David Albert, Structures for improving heat dissipation in stacked semiconductor packages.
상세보기
Halahan, Patrick B., Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity.
상세보기
Rostoker Michael D. (Boulder Creek CA), Techniques for providing high I/O count connections to semiconductor dies.
상세보기
Distefano Thomas H., Thermally enhanced packaged semiconductor assemblies.
상세보기
Chen, Eing-Chieh; Lai, Cheng-Yuan; Tien, Tzu-Yi, Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same.
상세보기
Eing-Chieh Chen TW; Cheng-Yuan Lai TW; Tzu-Yi Tien TW, Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same.
상세보기
Hawke Robert E.,CAX ; Patel Atin J.,CAX ; Binapal Sukhminder S.,CAX ; Divita Charles,CAX ; McNeil Lynn,CAX ; Fletcher Thomas G.,CAX, Three dimensional packaging configuration for multi-chip module assembly.
상세보기
Lin Paul T. (Austin TX), Three-dimensional multi-chip pad array carrier.
상세보기
Massit Claude (Ismier FRX) Nicolas Grard (Voreppe FRX), Three-dimensional multichip module.
상세보기
Burns Carmen D. (Austin TX) Roane Jerry (Austin TX) Cady James W. (Austin TX), Ultra high density integrated circuit packages.
상세보기

이 특허를 인용한 특허 (6) 인용/피인용 타임라인 분석

Brauchler, Fred T.; Gray, Randall C., Die-to-die inductive communication devices and methods.
상세보기
Brauchler, Fred T.; Pigott, John M.; Frear, Darrel R.; Gupta, Vivek; Gray, Randall C.; Owens, Norman L.; D'Acosta, Carl E., Die-to-die inductive communication devices and methods.
상세보기
Higgins, III, Leo M.; Brauchler, Fred T., Die-to-die inductive communication devices and methods.
상세보기
Choi, DaeSik; Ha, Jong-Woo; Kim, Seung Won, Integrated circuit packaging system with step mold and method of manufacture thereof.
상세보기
Brauchler, Fred T.; Gray, Randall C., Methods of manufacturing and operating die-to-die inductive communication devices.
상세보기
Pagaila, Reza Argenty; Camacho, Zigmund Ramirez; Bathan, Henry Descalzo, Package system with a shielded inverted internal stacking module and method of manufacture thereof.
상세보기

활용도 분석정보

상세보기

다운로드

내보내기

활용도 Top5 특허

해당 특허가 속한 카테고리에서 활용도가 높은 상위 5개 콘텐츠를 보여줍니다.
더보기 버튼을 클릭하시면 더 많은 관련자료를 살펴볼 수 있습니다.

IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

[미국특허] Multiple chip package module including die stacked over encapsulated package 원문보기

초록

대표청구항 ▼

연구과제 타임라인

이 특허에 인용된 특허 (112) 인용/피인용 타임라인 분석

이 특허를 인용한 특허 (6) 인용/피인용 타임라인 분석

활용도 분석정보

활용도 Top5 특허

관련 콘텐츠

특허 원문 보기

IPC 상위 출원인

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

선택된 텍스트

연합인증

[미국특허] Multiple chip package module including die stacked over encapsulated package 원문보기

초록

대표청구항 ▼

연구과제 타임라인

전체(0) 논문(0) 특허(0) 보고서(0)

전체(0) 논문(0) 특허(0) 보고서(0)

이 특허에 인용된 특허 (112) 인용/피인용 타임라인 분석

이 특허를 인용한 특허 (6) 인용/피인용 타임라인 분석

활용도 분석정보

활용도 Top5 특허 더보기

관련 콘텐츠

특허 원문 보기

IPC 상위 출원인

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

선택된 텍스트

활용도 Top5 특허