IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
UP-0404706
(2003-03-31)
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등록번호 |
US-7590829
(2009-09-24)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
2 인용 특허 :
84 |
초록
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A processor system. The processor system comprises a processor having a first set of instructions associated therewith. The processor system also comprises a programmable logic device and an extension adapter coupled to the processor and the programmable logic device. The extension adapter allows th
A processor system. The processor system comprises a processor having a first set of instructions associated therewith. The processor system also comprises a programmable logic device and an extension adapter coupled to the processor and the programmable logic device. The extension adapter allows the programmable logic device to implement a second set of reconfigurable instructions for the processor.
대표청구항
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What is claimed is: 1. A processor system, comprising: a processor configured to execute at least one of a set of standard instructions; a programmable logic device configured to execute at least one of a set of reconfigurable instructions; and an extension adapter coupled to the processor and the
What is claimed is: 1. A processor system, comprising: a processor configured to execute at least one of a set of standard instructions; a programmable logic device configured to execute at least one of a set of reconfigurable instructions; and an extension adapter coupled to the processor and the programmable logic device, the extension adapter configured to identify an instruction as either a standard instruction or a reconfigurable instruction and to provide a signal for an identified reconfigurable instruction, the signal configured to control the type of task performed on data in the programmable logic device or the timing of execution of the identified reconfigurable instruction, the extension adapter further configured to provide a signal indicating to the processor that the identified reconfigurable instruction is one of the set of standard instructions of the processor and that the extension adapter will handle processing the instruction instead of the processor. 2. The processor system of claim 1, wherein the programmable logic device includes a diagnostic interface configured for testing the programmable logic device. 3. The processor system of claim 1, wherein the processor system comprises a plurality of separate programmable logic devices coupled to the extension adapter. 4. The processor system of claim 1, wherein the extension adapter is further configured to control the flow of a result of the identified reconfigurable instruction from the programmable logic device to the processor. 5. The processor system of claim 1, wherein the extension adapter is further configured to check the validity of the at least one of the set of reconfigurable instructions each time the at least one of the set of reconfigurable instructions is received by the extension adapter. 6. The processor system of claim 1, wherein the extension adapter is configured to stall the processor if the programmable logic device is not ready to receive the identified reconfigurable instruction. 7. The processor system of claim 1, wherein the extension adapter is configured to notify the processor if an invalid instruction is received from the processor. 8. The processor system of claim 1, wherein the control of the timing of execution of the identified reconfigurable instruction includes managing timing relationships between register reads and register writes. 9. The processor system of claim 8, wherein the timing relationships between register reads and register writes are dependent on instruction execution time of the identified reconfigurable instruction. 10. The processor system of claim 1, wherein the extension adapter is configured to suppress a pipelined write from an earlier member of the set of reconfigurable instructions if the pipelined write is superseded by a later member of the set of reconfigurable instructions. 11. The processor system of claim 1, wherein the extension adapter is configured such that the processor treats members of the set of reconfigurable instructions as if they were defined pre-silicon. 12. The processor system of claim 1, wherein the extension adapter is further configured to use a standard load instruction of the processor to move data into a register file and to use a member of the set of reconfigurable instructions to move the data from the register file to the programmable logic device under the control of the extension adapter. 13. The processor system of claim 1, wherein the extension adapter is programmable post-silicon. 14. The processor system of claim 1, wherein the extension adaptor includes a programmable configuration memory configured to store a description of the at least one of the set of reconfigurable instructions. 15. The processor system of claim 14, wherein the extension adapter is further configured to use the description of the at least one of the set of reconfigurable instructions such that the at least one of the set of reconfigurable instructions appears to the processor to be identical in form to a standard instruction of the processor. 16. The processor system of claim 14, wherein the description of the at least one of the set of reconfigurable instructions includes an address of data needed by the at least one of the set of reconfigurable instructions. 17. The processor system of claim 1, further including a configuration memory configured to store data for use by the extension adapter to provide the signal to control the type of task performed on data in the programmable logic device or the timing of execution of the identified reconfigurable instruction. 18. A processor system, comprising: a processor configured to execute at least one of a set of standard instructions; a programmable logic device configured to execute at least one of a set of reconfigurable instructions; and an extension adapter coupled to the processor and the programmable logic device, the extension adapter configured to identify an instruction as either a standard instruction or a reconfigurable instruction and to provide a signal for an identified reconfigurable instruction, the signal configured to control the type of task performed on data in the programmable logic device or the timing of execution of the identified reconfigurable instruction, wherein the extension adapter comprises a first pipeline and a second pipeline, the first pipeline configured to receive data from the processor, the second pipeline configured to receive data from the programmable logic device. 19. The processor system of claim 18, wherein the second pipeline includes a plurality of insertion points and is further configured to receive the data at an insertion point selected by the extension adapter. 20. The processor system of claim 19, wherein the extension adapter is further configured to determine the selected insertion point based on decoding of an opcode included in the identified reconfigurable instruction. 21. The processor system of claim 18, wherein the first pipeline is shorter than the second pipeline. 22. The processor system of claim 21, wherein the first pipeline advances data at a first frequency and the second pipeline advances data at a second frequency. 23. The processor system of claim 22, wherein a plurality of outputs from the set of reconfigurable instructions are written to a plurality of register files within the extension adaptor. 24. The processor system of claim 18, wherein the extension adapter is configured to interface a first clock associated with the processor to the first pipeline and a second clock associated with the programmable logic device to the second pipeline. 25. A method for operating a processor system, the method comprising: receiving at least one of a set of standard instructions and at least one of a set of reconfigurable instructions; executing the at least one of a set of standard instructions in a processor; identifying in an extension adapter a received instruction as either a standard instruction or a reconfigurable instruction; providing a signal for an identified reconfigurable instruction from the extension adapter to a programmable logic device, the signal configured to control the type of task performed on data or the timing of execution of the at least one of the set of reconfigurable instructions in the programmable logic device; executing the identified reconfigurable instructions in the programmable logic device; and providing a signal from the extension adapter to the processor indicating to the processor that the identified reconfigurable instruction is one of the set of standard instructions of the processor and that the extension adapter will process the instruction instead of the processor. 26. The method of claim 25, further comprising recognizing and decoding in the extension adapter the set of identified reconfigurable instructions and wherein the provided signal is configured to enable data to be transferred between the processor and the programmable logic device. 27. The method of claim 25, wherein a plurality of programmable logic devices are coupled to the extension adapter. 28. A method for operating a processor system, the method comprising: receiving at least one of a set of standard instructions and at least one of a set of reconfigurable instructions; executing the at least one of a set of standard instructions in a processor; identifying in an extension adapter a received instruction as either a standard instruction or a reconfigurable instruction; providing a signal for an identified reconfigurable instruction from the extension adapter to a programmable logic device, the signal configured to control the type of task performed on data or the timing of execution of the at least one of the set of reconfigurable instructions in the programmable logic device; executing the identified reconfigurable instructions in the programmable logic device; and inserting data from the processor into a first pipeline and inserting data from the reconfigurable logic device into a second pipeline. 29. The method of claim 28, wherein the inserting data into the second pipeline includes selecting an insertion point from a plurality of insertion points in the second pipeline and inserting data into the selected insertion point. 30. The method of claim 28 further comprising advancing data in the first pipeline at a first frequency and advancing data in the second pipeline at a second frequency. 31. The method of claim 28, wherein the second pipeline is longer than the first pipeline. 32. The method of claim 28, further comprising interfacing a first clock associated with the processor to the first pipeline and interfacing a second clock associated with the programmable logic device to the second pipeline. 33. The method of claim 32, wherein the first clock has a frequency greater than or equal to that of the second clock. 34. The method of claim 32, wherein the first clock has a frequency that is a multiple of that of the second clock. 35. A processor system, comprising: means for executing at least one of a set of standard instructions in a processor; means for executing at least one of a set of reconfigurable instructions; and means for identifying an instruction as either a standard instruction or a reconfigurable instruction and providing for an identified reconfigurable instruction a signal for controlling the type of task performed on data in the reconfigurable instruction execution means or the timing of the at least one of the set of reconfigurable instructions. 36. The processor system of claim 35, wherein the identification means comprises means for recognizing and decoding the set of reconfigurable instructions and configuring the provided signal to enable data to be transferred between the standard instruction execution means and the reconfigurable instruction execution means. 37. The processor system of claim 35, wherein the set of standard instructions are fixed pre-silicon. 38. The processor system of claim 35, wherein the set of reconfigurable instructions are reconfigurable post-silicon. 39. The processor system of claim 35, wherein the means for identifying an instruction is configured to provide a signal to the standard instruction execution means indicating that the identified reconfigurable instruction is one of the set of standard instructions and that the means for identifying the instruction will process the identified instruction instead of the standard instruction execution means. 40. The processor system of claim 35, wherein the means for identifying an instruction includes a first means for pipelining data coupled to the standard instruction execution means and a second means for pipelining data coupled to the reconfigurable instruction execution means. 41. The processor system of claim 35, further comprising a first clock associated with the first pipelining means and a second clock associated with the second pipelining means. 42. The processor system of claim 41, wherein the first clock has a frequency that is a multiple of that of the second clock. 43. An extension adapter configured to be coupled to a processor configured to execute at least one of a set of standard instructions and to a programmable logic device configured to execute at least one of a set of reconfigurable instructions, the extension adapter further configured to identify an instruction as either a standard instruction or a reconfigurable instruction and to provide a signal for an identified reconfigurable instruction, the signal configured to control the type of task performed on data in the programmable logic device or timing of execution of the identified reconfigurable instruction, wherein the extension adapter includes a first pipeline and a second pipeline, the first pipeline configured to receive data from the processor, the second pipeline configured to receive data from the programmable logic device. 44. The extension adapter of claim 43, wherein the set of standard instructions are fixed pre-silicon. 45. The extension adapter of claim 43, wherein the set of reconfigurable instructions are reconfigurable post-silicon. 46. The extension adapter of claim 43, wherein the set of reconfigurable instructions appear to the processor to function as fixed pre-silicon instructions. 47. The extension adapter of claim 43, wherein the extension adapter comprises an interface configured to receive a first clock signal for advancing data through the first pipeline and associated with the processor and to receive a second clock signal for advancing data through the second pipeline and associated with the programmable logic device. 48. The extension adapter of claim 47, wherein the first clock has a frequency greater than or equal to that of the second clock. 49. The extension adapter of claim 47, wherein the first clock has a frequency that is a multiple of that of the second clock.
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