[특허]Methods of fabricating transistors including supported gate electrodes

[미국특허] Methods of fabricating transistors including supported gate electrodes 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/338 H01L-021/02
출원번호	UP-0333726 (2006-01-17)
등록번호	US-7592211 (2009-10-20)
발명자 / 주소	Sheppard, Scott T. Allen, Scott
출원인 / 주소	Cree, Inc.
대리인 / 주소	Myers Bigel Sibley & Sajovec, P.A.
인용정보	피인용 횟수 : 70 인용 특허 : 128

초록 ▼

Transistors are fabricated by forming a protective layer having an opening extending therethrough on a substrate, and forming a gate electrode in the opening. A first portion of the gate electrode laterally extends on surface portions of the protective layer outside the opening, and a second portion of the gate electrode is spaced apart from the protective layer and laterally extends beyond the first portion. Related devices and fabrication methods are also discussed.

대표청구항 ▼

That which is claimed is: 1. A method of fabricating a transistor, the method comprising: forming a first layer, wherein the first layer comprises a dielectric material; forming a second layer on the first layer, wherein the second layer has a hole therein exposing a portion of the first layer; forming a first opening extending through the first layer using the second layer as a mask; after forming the first opening, widening the hole in the second layer to form a second opening exposing the first opening and exposing surface portions of the first layer on opposite sides of the first opening; and forming a gate electrode in the first and second openings, wherein first portions of the gate electrode extend on surface portions of the first layer outside the first opening and second portions of the gate electrode extend on surface portions of the second layer outside the second opening. 2. The method of claim 1, wherein the first portions of the gate electrode laterally extend on surface portions of the first layer outside the first opening, wherein the second portions of the gate electrode laterally extend on the surface portions of the second layer outside the second opening beyond the first portions of the gate electrode. 3. The method of claim 1, wherein forming the gate electrode further comprises: forming the gate electrode in the first opening directly on opposing sidewalls thereof. 4. The method of claim 1, wherein the first layer comprises silicon nitride, aluminum nitride, and/or silicon dioxide. 5. The method of claim 1, wherein the first layer and the second layer comprise different materials, and wherein the second layer comprises a material having a lower dielectric index than the first layer. 6. The method of claim 1, wherein widening the hole in the second layer comprises: symmetrically expanding the hole in the second layer so that the second opening and the first opening are self-aligned. 7. The method of claim 1, wherein the second layer comprises a photoresist layer. 8. The method of claim 7 wherein widening the hole in the second layer comprises: ashing the second layer using an oxygen plasma and/or hard baking the second layer. 9. The method of claim 1, wherein widening the hole in the second layer comprises selectively etching the second layer using a wet etch to form the second opening therein. 10. The method of claim 1, further comprising: forming a channel layer; and forming a barrier layer on the channel layer, wherein forming the first layer comprises forming the first layer on the barrier layer, wherein forming the gate electrode comprises forming the gate electrode extending through the first opening in the first layer to contact the barrier layer, and wherein a junction between the channel layer and the barrier layer define a heterojunction. 11. The method of claim 1, further comprising: removing the second layer after forming the gate electrode. 12. The method of claim 11, further comprising: forming a passivation layer on the first layer and on the gate electrode after removing the second layer. 13. A method of fabricating a transistor, the method comprising: forming a channel layer; forming a barrier layer on the channel layer, wherein a junction between the channel layer and the barrier layer define a heterojunction; forming a protective layer on the barrier layer, the protective layer having an opening extending therethrough; forming first and second ohmic contact regions on the barrier layer adjacent to and spaced apart from the protective layer so that the protective layer is between the first and second ohmic contact regions; and forming a gate electrode extending through the opening in the protective layer to contact the barrier layer and so that a first portion of the gate electrode laterally extends on surface portions of the protective layer outside the opening and so that a second portion of the gate electrode spaced apart from the protective layer laterally extends beyond the first portion, wherein forming the first and second ohmic contact regions comprises: patterning the protective layer to expose portions of the barrier layer; forming ohmic metal regions on the exposed portions of the barrier layer adjacent to and spaced apart from the patterned protective layer; and annealing the ohmic metal regions.

이 특허에 인용된 특허 (128) 인용/피인용 타임라인 분석

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[미국특허] Methods of fabricating transistors including supported gate electrodes 원문보기

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