초록 ▼

A packet switch includes a packet processor for processing data packets. The packet processor receives a data packet including a data payload, identifies data portions in the data payload, and determines a destination address for each data portion. Additionally, the packet processor constructs data

A packet switch includes a packet processor for processing data packets. The packet processor receives a data packet including a data payload, identifies data portions in the data payload, and determines a destination address for each data portion. Additionally, the packet processor constructs data packets, each including a data portion and the destination address of the data portion. The packet processor then routes each of the constructed data packets based on a destination identifier of the constructed data packet. An external recipient can then store the data portions of the constructed data packets based on the data addresses in the constructed data packets.

대표청구항 ▼

What is claimed is: 1. A method of processing a data packet in a packet switch, the method comprising: receiving a first data packet by the packet switch, the first data packet comprising a destination identifier and a data payload; identifying a first data portion in the data payload of the first

What is claimed is: 1. A method of processing a data packet in a packet switch, the method comprising: receiving a first data packet by the packet switch, the first data packet comprising a destination identifier and a data payload; identifying a first data portion in the data payload of the first data packet; identifying a second data portion in the data payload of the first data packet; performing a data operation on the data payload of the first data packet for separating the first data portion from the second data portion; determining a destination address for the first data portion; determining a destination address for the second data portion; constructing a second data packet comprising the destination address of the first data portion and a data payload comprising the first data portion but not the second data portion; constructing a third data packet comprising the destination address of the second data portion and a data payload comprising the second data portion but not the first data portion; and routing the second data packet based on a destination identifier of the first data packet; and routing the third data packet based on a destination identifier of the second data packet, wherein the destination identifier of the second data packet and the destination identifier of the third data packet are the same destination identifier. 2. The method of claim 1, wherein the data operation includes a deinterleave operation for deinterleaving the first data portion and the second data portion. 3. The method of claim 1, further comprising: transmitting the second data packet from the packet switch to a digital signal processor; and transmitting the third data packet from the packet switch to the digital signal processor. 4. The method of claim 1, further comprising: transmitting the second data packet from the packet switch to a digital signal processor; transmitting the third data packet from the packet switch to the digital signal processor, storing the second data packet in a first data buffer of the digital signal processor based on the destination address of the second data packet; and storing the third data packet in a second data buffer of the digital signal processor based on the destination address of the third data packet. 5. The method of claim 1, wherein the destination address of the second data packet and the destination address of the third data packet are unique. 6. The method of claim 1, wherein determining the destination address of the second data packet comprises determining a start address, the start address being the destination address of the second data packet. 7. The method of claim 6, further comprising determining an address offset, wherein determining the destination address of the third data packet comprises summing the address offset and the start address. 8. The method of claim 7, further comprising: identifying a third data portion in the data payload of the first data packet; determining a stop address; determining the destination address of the second data packet is the same as the stop address; determining a destination address of the third data portion, the destination address of the third data portion being the start address; constructing a fourth data packet comprising the destination address of the third data portion and a data payload comprising the third data portion; and routing the fourth data packet based on a destination identifier of the fourth data packet, wherein the destination identifier of the second data packet, the destination identifier of the third data packet and the destination identifier of the fourth data packet are the same destination identifier. 9. The method of claim 1, wherein the data payload of the second data packet consists of the first data portion, and the data payload of the third data packet consists of the second data portion. 10. A packet switch, comprising: an input interface configured to receive a first data packet comprising a destination identifier and a data payload; and a packet processor coupled to the input interface, the packet processor configured to identify a first data portion and a second data portion of the data payload of the first data packet, perform a data operation on the data payload of the first data packet for separating the first data portion from the second data portion, determine a destination address for each of the first data portion and the second data portion, construct a second data packet comprising the destination address of the first data portion and a data payload comprising the first data portion but not the second data portion, construct a third data packet comprising the destination address of the second data portion and a data payload comprising the second data portion but not the first data portion, route the second data packet based on a destination identifier of the second data packet, and route the third data packet based on a destination identifier of the third data packet, wherein the destination identifier of the second data packet and the destination identifier of the third data packet are the same destination identifier. 11. The packet switch of claim 10, wherein the packet processor is further configured to determine a start address and an address offset, the start address being the destination address of the second data packet, the packet processor further configured to determine the destination address of the third data packet by summing the address offset and the start address. 12. The packet switch of claim 10, wherein the data operation includes a deinterleave operation for deinterleaving the first data portion and the second data portion. 13. The packet switch of claim 10, further comprising an output interface coupled to the packet processor and a digital signal processor, the output interface configured to transmit the second data packet and the third data packet to the digital signal processor. 14. The packet switch of claim 13, wherein the digital signal processor comprises a first data buffer and a second data buffer, and wherein the digital signal processor is configured to store the second data packet in the first data buffer based on the destination address of the second data packet and to store the third data packet in the second data buffer based on the destination address of the third data packet. 15. The packet switch of claim 10, wherein the destination address of the second data packet and the destination address of the third data packet are unique. 16. The packet switch of claim 10, wherein the data payload of the second data packet consists of the first data portion, and the data payload of the third data packet consists of the second data portion. 17. A packet switch, comprising: means for receiving a first data packet comprising a destination identifier and a data payload; means for identifying a first data portion in the data payload of the first data packet; means for identifying a second data portion in the data payload of the first data packet; means for performing a data operation on the first data packet for separating the first data portion from the second data portion; means for determining a destination address for the first data portion; means for determining a destination address for the second data portion; means for constructing a second data packet comprising the destination address of the first data portion and a data payload comprising the first data portion but not the second data portion; means for constructing a third data packet comprising the destination address of the second data portion and a data payload comprising the second data portion but not the first data portion; means for routing the second data packet based on a destination identifier of the first data packet; and means for routing the third data packet based on a destination identifier of the second data packet, wherein the destination identifier of the second data packet and the destination identifier of the third data packet are the same destination identifier. 18. The packet switch of claim 17, further comprising: means for transmitting the second data packet to a digital signal processor coupled to the packet switch; means for transmitting the third data packet to the digital signal processor; means for storing the second data packet in the digital signal processor based on the destination address of the second data packet; and means for storing the third data packet in the digital signal processor based on the destination address of the third data packet. 19. The packet switch of claim 18, wherein the data payload of the second data packet consists of the first data portion, and the data payload of the third data packet consists of the second data portion. 20. The method of claim 1, wherein the data operation includes an interleave operation for interleaving the first data portion and the second data portion. 21. The method of claim 1, wherein the data operation includes a sign extend operation for extending a sign data bit of the first data portion and extending a sign data bit of the second data portion. 22. The method of claim 1, wherein the data operation includes a data flip operation for flipping data bits of the first data portion and flipping data bits of the second data portion. 23. The method of claim 1, wherein the data operation includes a post dynamic ranging operation for truncating at least one most significant data bit of the first data portion and truncating at least one most significant data bit of the second data portion. 24. The method of claim 1, wherein the data operation includes a data reorder operation for reordering the first data portion and the second data portion.