초록 ▼

An oscillator is provided that includes an oscillating structure generating an output signal with a frequency that drifts as a function of a parameter of its environment, and a compensation circuit coupled to the oscillating structure. The oscillating structure has a ring structure that includes del

An oscillator is provided that includes an oscillating structure generating an output signal with a frequency that drifts as a function of a parameter of its environment, and a compensation circuit coupled to the oscillating structure. The oscillating structure has a ring structure that includes delay cells looped together, and the compensation circuit supplies a compensation signal to the oscillating structure. The compensation signal varies as a function of changes in the parameter in order to compensate for the drift in the frequency of the generated signal. This makes it possible to compensate for oscillator temperature drifts in the absence of a regulation loop.

대표청구항 ▼

What is claimed is: 1. An oscillator comprising: an oscillating structure with a ring structure, the oscillating structure including at least one first transistor of the PMOS type with its source coupled to a positive power supply node and its gate receiving a cell oscillation frequency control vol

What is claimed is: 1. An oscillator comprising: an oscillating structure with a ring structure, the oscillating structure including at least one first transistor of the PMOS type with its source coupled to a positive power supply node and its gate receiving a cell oscillation frequency control voltage, and a plurality of delay cells looped together, the oscillator generating an output signal with a frequency that drifts as a function of the temperature of its environment, each of the delay cells including: a first resistance coupled between the positive power supply node and a first output; a second resistance coupled between the positive power supply node and a second output; a second transistor of the PMOS type with its gate coupled to the second output, its source coupled to the drain of the first transistor and its drain coupled to the first output; a third transistor of the PMOS type with its gate coupled to the first output, its source coupled to the drain of the first transistor and its drain coupled to the second output; a fourth transistor of the NMOS type with its gate coupled to a first input such that the fourth transistor is controlled based on a voltage at the first input, the drain of the fourth transistor being coupled to the first output and the source of the fourth transistor being coupled to a ground node; and a fifth transistor of the NMOS type with its gate coupled to a second input such that the fifth transistor is controlled based on a voltage at the second input, the drain of the fifth transistor being coupled to the second output and the source of the fifth transistor being coupled to the ground node; and a compensation circuit coupled to the oscillating structure, the compensation circuit supplying a temperature compensation current that grows with the temperature to the first and second resistances of the delay cells in order to compensate for the drift in the frequency of the output signal generated by the oscillator. 2. The oscillator according to claim 1, wherein the compensation circuit includes: a sixth transistor that is diode-connected and has its first electrode coupled to the positive power supply node; a seventh transistor with its first electrode coupled to the positive power supply node, its second electrode supplying the temperature compensation current and its control electrode coupled to a control electrode of the sixth transistor; and an eighth transistor with its first electrode coupled to a second electrode of the sixth transistor and its second electrode coupled to the ground node. 3. The oscillator according to claim 2, wherein the first electrode of the sixth transistor is coupled to the positive power supply node through a third resistance. 4. The oscillator according to claim 3, wherein the first electrode of the seventh transistor is coupled to the positive power supply node through a fourth resistance. 5. The oscillator according to claim 3, wherein the first electrode of the seventh transistor is coupled to the positive power supply node through a ninth transistor that is diode-connected. 6. The oscillator according to claim 5, wherein the second electrode of the seventh transistor is coupled to the second electrode of the eighth transistor through a capacitor. 7. The oscillator according to claim 2, wherein the second electrode of the seventh transistor is coupled to the second electrode of the eighth transistor through a capacitor. 8. The oscillator according to claim 2, wherein the sixth, seventh and eighth transistors are transistors of the PMOS type. 9. A phase-locked loop comprising: an oscillator including: an oscillating structure with a ring structure, the oscillating structure including at least one first transistor of the PMOS type with its source coupled to a positive power supply node and its gate receiving a cell oscillation frequency control voltage, and a plurality of delay cells looped together, the oscillator generating an output signal with a frequency that drifts as a function of the temperature of its environment, each of the delay cells including: a first resistance coupled between the positive power supply node and a first output; a second resistance coupled between the positive power supply node and a second output; a second transistor of the PMOS type with its gate coupled to the second output, its source coupled to the drain of the first transistor and its drain coupled to the first output; a third transistor of the PMOS type with its gate coupled to the first output, its source coupled to the drain of the first transistor and its drain coupled to the second output; a fourth transistor of the NMOS type with its gate coupled to a first input such that the fourth transistor is controlled based on a voltage at the first input, the drain of the fourth transistor being coupled to the first output and the source of the fourth transistor being coupled to a ground node; and a fifth transistor of the NMOS type with its gate coupled to a second input such that the fifth transistor is controlled based on a voltage at the second input, the drain of the fifth transistor being coupled to the second output and its the source of the fifth transistor being coupled to the ground node; and a compensation circuit coupled to the oscillating structure, the compensation circuit supplying a temperature compensation current that grows with the temperature to the first and second resistances of the delay cells in order to compensate for the drift in the frequency of the output signal generated by the oscillator; a phase comparator receiving a reference signal and the output signal generated by the oscillator, the phase comparator generating an oscillation frequency control voltage as a function of the difference between the reference signal and the output signal generated by the oscillator; and a switch selectively placing the oscillator in an open loop or a closed loop. 10. The phase-locked loop according to claim 9, wherein the compensation circuit of the oscillator includes: a sixth transistor that is diode-connected and has its first electrode coupled to the positive power supply node; a seventh transistor with its first electrode coupled to the positive power supply node, its second electrode supplying the temperature compensation current and its control electrode coupled to a control electrode of the sixth transistor; and an eighth transistor with its first electrode coupled to a second electrode of the sixth transistor and its second electrode coupled to the ground node. 11. The phase-locked loop according to claim 10, wherein the first electrode of the sixth transistor of the compensation circuit of the oscillator is coupled to the positive power supply node through a third resistance. 12. The phase-locked loop according to claim 11, wherein the first electrode of the seventh transistor of the compensation circuit of the oscillator is coupled to the positive power supply node through a fourth resistance. 13. The phase-locked loop according to claim 11, wherein the first electrode of the seventh transistor of the compensation circuit of the oscillator is coupled to the positive power supply node through a ninth transistor that is diode-connected. 14. The phase-locked loop according to claim 10, wherein the second electrode of the seventh transistor of the compensation circuit of the oscillator is coupled to the second electrode of the eighth transistor of the compensation circuit of the oscillator through a capacitor. 15. A radio frequency send/receive device comprising: a send circuit; a receive circuit; an aerial coupled to the send circuit and the receive circuit; a phase-locked loop including: an oscillator including: an oscillating structure with a ring structure, the oscillating structure including at least one first transistor of the PMOS type with its source coupled to a positive power supply node and its gate receiving a cell oscillation frequency control voltage, and a plurality of delay cells looped together, the oscillator generating a radio frequency output signal with a frequency that drifts as a function of the temperature of its environment, each of the delay cells including: a first resistance coupled between the positive power supply node and a first output; a second resistance coupled between the positive power supply node and a second output; a second transistor of the PMOS type with its gate coupled to the second output, its source coupled to the drain of the first transistor and its drain coupled to the first output; a third transistor of the PMOS type with its gate coupled to the first output, its source coupled to the drain of the first transistor and its drain coupled to the second output; a fourth transistor of the NMOS type with its gate coupled to a first input such that the fourth transistor is controlled based on a voltage at the first input, the drain of the fourth transistor being coupled to the first output and the source of the fourth transistor being coupled to a ground node; and a fifth transistor of the NMOS type with its gate coupled to a second input such that the fifth transistor is controlled based on a voltage at the second input, the drain of the fifth transistor being coupled to the second output and the source of the fifth transistor being coupled to the ground node; and a compensation circuit coupled to the oscillating structure, the compensation circuit supplying a temperature compensation current that grows with the temperature to the first and second resistances of the delay cells in order to compensate for the drift in the frequency of the output signal generated by the oscillator; a phase comparator receiving a reference signal and the output signal generated by the oscillator, the phase comparator generating an oscillation frequency control voltage as a function of the difference between the reference signal and the output signal generated by the oscillator; and a switch selectively placing the oscillator in an open loop or a closed loop; and a control circuit for: placing the oscillator in an open loop, applying the output signal generated by the oscillator to the send circuit and coupling the send circuit to the aerial during a send phase; and placing the oscillator in a closed loop, applying the output signal generated by the oscillator to the receive circuit and coupling the receive circuit to the aerial during a receive phase. 16. The send/receive device according to claim 15, wherein the compensation circuit of the oscillator of the phase-locked loop includes: a sixth transistor that is diode-connected and has its first electrode coupled to the positive power supply node; a seventh transistor with its first electrode coupled to the positive power supply node, its second electrode supplying the temperature compensation current and its control electrode coupled to a control electrode of the sixth transistor; and an eighth transistor with its first electrode coupled to a second electrode of the sixth transistor and its second electrode coupled to the ground node. 17. The send/receive device according to claim 16, wherein the first electrode of the sixth transistor of the compensation circuit of the oscillator of the phase-locked loop is coupled to the positive power supply node through a third resistance. 18. The send/receive device according to claim 17, wherein the first electrode of the seventh transistor of the compensation circuit of the oscillator of the phase-locked loop is coupled to the positive power supply node through a fourth resistance. 19. The send/receive device according to claim 17, wherein the first electrode of the seventh transistor of the compensation circuit of the oscillator of the phase-locked loop is coupled to the positive power supply node through a ninth transistor that is diode-connected. 20. The send/receive device according to claim 16, wherein the second electrode of the seventh transistor of the compensation circuit of the oscillator of the phase-locked loop is coupled to the second electrode of the eighth transistor of the compensation circuit of the oscillator of the phase-locked loop through a capacitor. 21. The oscillator according to claim 1, wherein the first resistance is directly connected to the first output, and the second resistance is directly connected to the second output. 22. The oscillator according to claim 1, wherein the first resistance comprises a first resistor that is coupled between the compensation circuit and the first output, and the second resistance comprises a second resistor that is coupled between the compensation circuit and the second output. 23. The oscillator according to claim 1, wherein the gate of the fourth transistor is directly connected to the first input, and the gate of the fifth transistor is directly connected to the second input. 24. The oscillator according to claim 2, wherein the second electrode of the seventh transistor is directly connected to both the first resistance and the second resistance, and the compensation circuit supplies the temperature compensation current directly to the first and second resistances. 25. The oscillator according to claim 1, wherein the compensation circuit includes a seventh transistor with its first electrode coupled to the positive power supply node, and its second electrode directly connected to both the first resistance and the second resistance, and the second electrode of the seventh transistor supplies the temperature compensation current directly to the first and second resistances. 26. The oscillator according to claim 1, wherein the dram of the fourth transistor is directly connected to the drain of the second transistor and is directly connected to the first resistance, and the drain of the fifth transistor is directly connected to the drain of the third transistor and is directly connected to the second resistance. 27. The oscillator according to claim 1, wherein the first resistance has a first terminal that is directly connected to the first output and a second terminal that is directly connected to the compensation circuit and wherein the second resistance has a first terminal that is directly connected to the second output and a second terminal that is directly connected to the first terminal of the first resistance and directly connected to the compensation circuit. 28. The oscillator according to claim 1, wherein the first resistance has a first terminal that is coupled to the positive power supply node and the second resistance has a first terminal that is coupled to the positive power supply node, the compensation circuit supplies the temperature compensation current directly to the first terminal of the first resistance and the first terminal of the second resistance.