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Integrated circuit package with molded insulation 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/00
출원번호 UP-0614281 (2006-12-21)
등록번호 US-7608482 (2009-11-10)
발명자 / 주소
  • Bayan, Jaime
출원인 / 주소
  • National Semiconductor Corporation
대리인 / 주소
    Beyer Law Group LLP
인용정보 피인용 횟수 : 22  인용 특허 : 29

초록

A variety of improved arrangements and processes for packaging integrated circuits are described. More particularly, methods of encapsulating dice in lead frame based IC packages are described that facilitate covering some portions of the bottom surface of the lead frame while leaving other portions

대표청구항

What is claimed is: 1. A method of encapsulating integrated circuits mounted on a lead frame panel, the method comprising: positioning a shim in a mold, the shim having a plurality of cavities therein; positioning a lead frame panel having tape adhered to a bottom surface thereof in the mold such t

이 특허에 인용된 특허 (29)

  1. Islam,Shafidul; San Antonio,Romarico Santos; Subagio,Anang, Die pad for semiconductor packages and methods of making and using same.
  2. Mostafazadeh Shahram ; Smith Joseph O., Lead frame chip scale package.
  3. Lee, Hyung Ju, Lead frame for semiconductor package.
  4. Hatakeyama Koichi,JPX ; Sugawara Akira,JPX ; Kanzaki Toshihiro,JPX, Leadframe made of a high-strength, high-electroconductivity copper alloy.
  5. Lau,Keng Kiat, Leadframe with encapsulant guide and method for the fabrication thereof.
  6. Chien-Ping Huang TW, Leadless image sensor package structure and method for making the same.
  7. Frezza, Giovanni; Tiziani, Roberto, Leads of a no-lead type package of a semiconductor device.
  8. Michael A. Lamson ; Heping Yue ; Truong Ho, Low pass filter integral with semiconductor package.
  9. Janssen, Johannes Bernardus Petrus; de Vrught, Johannes Bernardus, Method for manufacturing encapsulated electronic components, particularly integrated circuits.
  10. Ma, Bao-Tong; Sarkhel, Amit Kumar; Seto, Ping Kwong, Method for producing circuit board assemblies using surface mount components with finely spaced leads.
  11. Fukaya,Syuudai; Shinya,Toshiyuki; Hasebe,Hajime, Method of manufacturing a semiconductor device.
  12. Thomas P. Glenn ; Scott J. Jewler ; David Roman ; J. H. Yee KR; D. H. Moon KR, Methods for moding a leadframe in plastic integrated circuit devices.
  13. Fukushima Yuichi (Saitama JPX) Kobayashi Fujio (Kanagawa JPX) Takahashi Shinichiro (Tokyo JPX), Mold for transfer molding.
  14. Jaime Bayan ; Peter Howard Spalding, Multi row leadless leadframe package.
  15. Bayan, Jaime; Spalding, Peter Howard, Multiple row fine pitch leadless leadframe package with use of half-etch process.
  16. Glenn Thomas P. ; Jewler Scott J. ; Roman David ; Yee J. H.,KRX ; Moon D. H.,KRX, Plastic integrated circuit device package and leadframe having partially undercut leads and die pad.
  17. Glenn, Thomas P.; Jewler, Scott J.; Roman, David; Yee, Jae Hak; Moon, Doo Hwan, Plastic integrated circuit device package and method for making the package.
  18. Glenn, Thomas P., Plastic integrated circuit package and leadframe for making the package.
  19. Thomas P. Glenn, Plastic integrated circuit package and method and leadframe for making the package.
  20. Yamada, Yuichiro; Minamio, Masanori, Resin-sealed semiconductor device.
  21. Yagi Hiroshi,JPX ; Sasaki Masato,JPX ; Togashi Kazuyoshi,JPX, Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device.
  22. Mclellan Neil,HKX ; Fan Nelson,HKX, Saw-singulated leadless plastic chip carrier.
  23. Mclellan Neil,HKX ; Fan Nelson,HKX, Saw-singulated leadless plastic chip carrier.
  24. Ito,Fujio; Suzuki,Hiromicti, Semiconductor device and method of manufacturing the same.
  25. Heung-su Gang KR, Semiconductor package having implantable conductive lands and method for manufacturing the same.
  26. Bayan,Jaime A.; Prabhu,Ashok S.; Lee,Shaw Wei, Solder pad configuration for use in a micro-array integrated circuit package.
  27. Mostafazadeh, Shahram, Substrate for semiconductor packaging.
  28. Bayan,Jaime; Prabhu,Ashok S.; Drummond,Fred, Substrate for use in semiconductor manufacturing and method of making same.
  29. Murtuza, Masood; Venkateswaran, Muthiah; Chauhan, Satyendra S., Using a supporting structure to control collapse of a die towards a die pad during a reflow process for coupling the die to the die pad.

이 특허를 인용한 특허 (22)

  1. Chen, Chien-Wen; Lai, Yi-Shao; Chang, Hsiao-Chuan; Tsai, Tsung-Yueh; Chien, Pao-Huei Chang; Hu, Ping-Cheng; Lee, Hsu-Yang, Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof.
  2. Chang Chien, Pao-Huei; Hu, Ping-Cheng; Chen, Chien-Wen, Advanced quad flat no lead chip package having marking and corner lead features and manufacturing methods thereof.
  3. Chang Chien, Pao-Huei; Hu, Ping-Cheng; Chiang, Po-Shing; Cheng, Wei-Lun, Advanced quad flat non-leaded package structure and manufacturing method thereof.
  4. Guo, Xiaowei; He, Wenhai; Mu, Wei; Wang, Xinjun, Carrier-free land grid array IC chip package and preparation method thereof.
  5. Kiew, Kelvin K., Circuit system in a package.
  6. Ishibashi, Takahiro, Lead frame.
  7. Nondhasitthichai, Somchai; Sirinorakul, Saravuth; Kongthaworn, Kasemsan; Suwannaset, Vorajit, Lead frame ball grid array with traces under die.
  8. Nondhasitthichai, Somchai; Sirinorakul, Saravuth; Kongthaworn, Kasemsan; Suwannaset, Vorajit, Lead frame ball grid array with traces under die.
  9. Sirinorakul, Saravuth, Lead frame ball grid array with traces under die having interlocking features.
  10. Sirinorakul, Saravuth, Lead frame ball grid array with traces under die having interlocking features.
  11. Nondhasitthichai, Somchai; Sirinorakul, Saravuth; Kongthaworn, Kasemsan; Suwannaset, Vorajit, Lead frame land grid array with routing connector trace under unit.
  12. Nondhasitthichai, Somchai; Sirinorakul, Saravuth; Kongthaworn, Kasemsan; Suwannaset, Vorajit, Lead frame land grid array with routing connector trace under unit.
  13. Chang Chien, Pao-Huei; Hu, Ping-Cheng; Chiang, Po-Shing; Cheng, Wei-Lun, Manufacturing method of advanced quad flat non-leaded package.
  14. Nondhasitthichai, Somchai; Sirinorakul, Saravuth, Method for forming lead frame land grid array.
  15. Park, DongSam; Yang, JoungIn, Package-on-package system with through vias and method of manufacture thereof.
  16. Koga, Akihiro; Nagahara, Toichi, Semiconductor device.
  17. Koga, Akihiro; Nagahara, Toichi, Semiconductor device.
  18. Koga, Akihiro; Nagahara, Toichi, Semiconductor device.
  19. Koga, Akihiro; Nagahara, Toichi, Semiconductor device.
  20. Chang Chien, Pao-Huei; Hu, Ping-Cheng; Chiang, Po-Shing; Cheng, Wei-Lun, Semiconductor package and manufacturing method thereof.
  21. Chien, Pao-Huei Chang; Hu, Ping-Cheng; Chen, Chien-Wen; Lee, Hsu-Yang, Semiconductor package having a cavity structure.
  22. Lu, Chun-Ting; Lin, Chun-Hung; Chen, Yi-Ting, Semiconductor packages and related manufacturing methods.
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