초록 ▼

A decoding system decodes forward error correction (FEC) encoded data. Factor graph circuitry (such as trellis decoder circuitry) processes the FEC encoded data according to at least one factor graph. Order restoring circuitry (such as convolutional deinterleaver circuitry) is coupled to an output

A decoding system decodes forward error correction (FEC) encoded data. Factor graph circuitry (such as trellis decoder circuitry) processes the FEC encoded data according to at least one factor graph. Order restoring circuitry (such as convolutional deinterleaver circuitry) is coupled to an output of the factor graph circuitry and restores ordering of symbols in the encoded data. Error detection and correction circuitry is coupled to an output of the order restoring circuitry and processes block-based error correcting codes to detect and correct errors in the FEC encoded data and to provide a hard-decision output to an output of the decoding system. Feedback circuitry (such as convolutional interleaver circuitry and symbol interleaver circuitry) is coupled to process the hard-decision output from the error correction and detection circuitry and to provide the processed hard-decision output to the factor graph circuitry.

대표청구항 ▼

What is claimed is: 1. A decoding system, configured to decode forward error correction (FEC) encoded data that has been encoded using a concatenated Reed-Solomon code and trellis code scheme, comprising: trellis decoder circuitry configured to process the encoded data according to path portions of

What is claimed is: 1. A decoding system, configured to decode forward error correction (FEC) encoded data that has been encoded using a concatenated Reed-Solomon code and trellis code scheme, comprising: trellis decoder circuitry configured to process the encoded data according to path portions of at least one trellis graph; order restoring circuitry coupled to an output of the trellis decoder circuitry configured to restore ordering of symbols in the encoded data; Reed-Solomon error detection and correction circuitry coupled to an output of the order restoring circuitry, configured to process block-based error correcting codes in data from the trellis decoder circuitry to detect and correct errors in the FEC encoded data, and further configured to provide a hard-decision output as an output of the decoding system; and reordering circuitry coupled to an output of the Reed-Solomon error detection and correction circuitry and configured to reorder the hard-decision output and to provide the reordered hard-decision output to the trellis decoder circuitry; wherein the trellis decoder circuitry is configured to choose one or more path portions of the at least one trellis graph indicated by the hard-decision output from the Reed-Solomon error detection and correction circuitry, and wherein an output of the trellis decoder circuitry depends, at least in part, on the chosen one or more path portions. 2. The decoding system of claim 1, wherein the reordering circuitry is configured to reorder the hard-decision output by convolving and interleaving the hard-decision output from the Reed-Solomon error detection and correction circuitry. 3. A decoding system, configured to decode forward error correction (FEC) encoded data, comprising: factor graph decoding circuitry configured to process the encoded data according to particular path portions of at least one factor graph; order restoring circuitry coupled to an output of the factor graph decoding circuitry and configured to restore ordering of symbols in the encoded data; error detection and correction circuitry coupled to an output of the order restoring circuitry, configured to process block-based error correcting codes to detect and correct errors in the encoded data, and further configured to provide a hard-decision output as an output of the decoding system; and feedback circuitry configured to process the hard-decision output and to provide the processed hard-decision output to the factor graph decoding circuitry; wherein the factor graph decoding circuitry is configured to choose particular path portions of the at least one factor graph based on the processed hard-decision output and to process the encoded data according to the chosen particular path portions. 4. The decoding system of claim 3, wherein the factor graph decoding circuitry includes trellis decoder circuitry configured to process the encoded data according to at least one trellis graph. 5. The decoding system of claim 4, wherein the feedback circuitry includes circuitry configured to convolve and interleave the hard-decision output and to provide the convolved interleaved hard-decision output to the trellis decoder circuitry. 6. The decoding system of claim 3, wherein the feedback circuitry includes circuitry configured to convolve and interleave the hard-decision output and to provide the convolved interleaved hard-decision output to the factor decoding circuitry. 7. The decoding system of claim 3, wherein the error detection and correction circuitry includes Reed-Solomon decoding circuitry. 8. The decoding system of claim 3, wherein: the factor graph decoding circuitry includes a plurality of path portions, wherein the path portions comprise one or more paths corresponding to possible decoding output of the factor graph circuitry; and the factor graph decoding circuitry is further configured to operate such that the output of the factor graph circuitry is based on the one or more path portions indicated by the processed hard-decision output. 9. The decoding system of claim 8, wherein the factor graph decoding circuitry is further configured to operate such that when the hard-decision output is not provided, the one or more path portions on which the output of the factor graph decoding circuitry is based is determined based on state metrics criteria. 10. A method of decoding encoded data with a decoder, wherein the data has been encoded using forward error correction (FEC) encoding, the method comprising: (a) processing the encoded data according to at least one factor graph; (b) processing block-based error correcting codes in a result of step (a) to detect and correct errors in the FEC encoded data and providing a hard-decision output based thereon; and (c) feeding back the hard-decision output from step (b) to provide the processed hard-decision output to subsequent instances of step (a); wherein the subsequent instances of step (a) include determining particular path portions of the at least one factor graph based, at least in parts, on the provided processed hard-decision output and processing the encoded data according to the determined particular path portions. 11. The method of claim 10, wherein said processing the encoded data includes processing the encoded data according to at least one trellis graph. 12. The method of claim 11, wherein said feeding back the hard-decision output from step (b) includes convolving and interleaving the hard decision output from step (b). 13. The method of claim 10, wherein said feeding back the hard-decision output from step (b) includes convolving and interleaving the hard decision output from step (b). 14. The method of claim 10, wherein step (b) includes processing the block-based error correcting codes according to Reed-Solomon decoding. 15. The method of claim 10, wherein step (a) further includes processing the factor graph such that when the hard-decision output is not provided from step (b), the particular path portions are determined based on state metrics criteria.