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Interconnect assemblies and methods 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-031/02
출원번호 UP-0669068 (2007-01-30)
등록번호 US-7618281 (2009-11-27)
발명자 / 주소
  • Eldridge, Benjamin N.
출원인 / 주소
  • FormFactor, Inc.
대리인 / 주소
    Burraston, N. Kenneth
인용정보 피인용 횟수 : 2  인용 특허 : 51

초록

Interconnect assemblies and methods for forming and using them. In one example of the invention, an interconnect assembly comprises a substrate, a resilient contact element and a stop structure. The resilient contact element is disposed on the substrate and has at least a portion thereof which is ca

대표청구항

What is claimed is: 1. A probe card assembly for use in testing a semiconductor wafer comprising a plurality of dies, the probe card assembly comprising: a substrate; a plurality of resilient, elongate contact elements extending from the substrate and configured to contact terminals of the semicond

이 특허에 인용된 특허 (51)

  1. Cooper,Timothy E.; Eldridge,Benjamin N.; Reynolds,Carl V.; Shenoy,Ravindra Vaman, Apparatus and method for limiting over travel in a probe card assembly.
  2. Farnworth Warren M. ; Akram Salman ; Wood Alan G. ; Hembree David R. ; Wark James M. ; Jacobson John O., Apparatus for testing semiconductor wafers.
  3. Dery Ronald A. (Winston-Salme NC), Area array connector for substrates.
  4. Oi Kenichi (Osaka JPX), Combined board construction for burn-in and burn-in equipment for use with combined board.
  5. Chan Benson ; Desai Kishor V. ; Sherman John H., Compliant, surface-mountable interposer.
  6. Rowlette John R. (Clemmons NC), Conductive gel interconnection apparatus.
  7. Herandez Jorge M. (1920 E. Jarvis Mesa AZ 85202) Simpson Scott S. (Senexet Rd. Woodstock CT 06281) Hyslop Michael S. (4147 W. Victoria La. Chandler AZ 85226), Device for interconnecting integrated circuit packages to circuit boards.
  8. Lundergan Robert G. (Camp Hill PA) Marks Richard L. (Mechanicsburg PA), Dual-in-line socket assembly.
  9. Dalamangas Chris A. (Union NJ) Piccirillo Thomas P. (North Plainfield NJ) Seip Donald P. (Bridgewater NJ), Electrical connector and support means therefor.
  10. Maeda Ryu (Urawa JPX) Tateishi Akira (Hachioji JPX) Tazai Shunsuke (Fuchu JPX), Electrical connectors using anisotropic conductive films.
  11. Eldridge, Benjamin N., Electrical interconnect assemblies and methods.
  12. Khandros, Igor Y.; Pedersen, David V.; Eldridge, Benjamin N.; Roy, Richard S.; Mathieu, Gaetan, Electronic component overlapping dice of unsingulated semiconductor wafer.
  13. Takamatsu Toshiaki (Tenri JPX) Funada Fumiaki (Yamatokoriyama JPX) Yasuda Shuhei (Nara JPX) Matsuura Masataka (Tenri JPX), Electronic component with plurality of terminals thereon.
  14. Eldridge Benjamin N. ; Khandros Igor Y. ; Mathieu Gaetan L. ; Pedersen David V., Electronic components with terminals and spring contact elements extending from areas which are remote from the terminals.
  15. Khandros Igor Y. ; Mathieu Gaetan L., Flexible contact structure with an electrically conductive shell.
  16. Bross Arthur (Poughkeepsie NY) Walsh Thomas J. (Poughkeepsie NY), High density electronic connector and method of assembly.
  17. Babuka, Robert; Piechota, John L.; Poch, Leonard J., High density planar interconnected integrated circuit package.
  18. Boll Gregory G. (Naples FL) Boll Harry J. (Naples FL), Integrated circuit probing apparatus including a capacitor bypass structure.
  19. Hines Clyde K. (Arcadia CA), Interchangeable test head for loaded test member.
  20. Eldridge, Benjamin N., Interconnect assemblies and methods.
  21. Eldridge,Benjamin N., Interconnect assemblies and methods.
  22. Khandros Igor Y. ; Pedersen David V. ; Eldridge Benjamin N. ; Roy Richard S. ; Mathieu Gaetan, Interconnect assemblies and methods including ancillary electronic component connected in immediate proximity of semiconductor device.
  23. Karnezos Marcos (Palo Alto CA), Interconnect structure for PC boards and integrated circuits.
  24. McDevitt ; Jr. John E. (Cumberland RI), Leadless grid array socket.
  25. Hopfer ; III Albert N. (Park Ridge IL) Lindeman Richard J. (Wood Dale IL), Low-loss electrical interconnects.
  26. Akram Salman ; Farnworth Warren M. ; Wood Alan G., Method for fabricating semiconductor components using focused laser beam.
  27. Farnworth Warren M. (Nampa ID) Akram Salman (Boise ID) Wood Alan G. (Boise ID), Method for forming contact pins for semiconductor dice and interconnects.
  28. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of making contact tip structures.
  29. Stern Herman Abraham (Somerville NJ), Method of making electrical connections for liquid crystal cells.
  30. Khandros Igor Y. (Peekskil NY), Method of manufacturing electrical contacts, using a sacrificial member.
  31. Khandros Igor Y., Method of mounting free-standing resilient electrical contact structures to electronic components.
  32. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of planarizing tips of probe elements of a probe card assembly.
  33. Swapp Mavin (Mesa AZ), Micromachined semiconductor probe card.
  34. Gabrielian Henry (Newport Beach CA), Miniature electrical connector.
  35. Myer Jon H. (Woodland Hills CA) Grinberg Jan (Los Angeles CA), Parallel interconnect for planar arrays.
  36. Swart Mark A. (Upland CA), Pneumatic test fixture with springless test probes.
  37. Herrell Dennis J. (Austin TX) Gupta Omkarnath R. (Englewood CO), Printed wire connector.
  38. Nakano Shoukichi (Kawasaki JPX), Prober for semiconductor integrated circuit element wafer.
  39. Hara Akitoshi (Suwa JPX), Semiconductor device and its manufacturing method.
  40. Otsuka Kanji (Higashiyamato JPX) Kato Masao (Hadano JPX) Kumagai Takashi (Isehara JPX) Usami Mitsuo (Ohme JPX) Kuroda Shigeo (Ohme JPX) Sahara Kunizo (Nishitama JPX) Yamada Takeo (Koganei JPX) Miyamo, Semiconductor device having leads for mounting to a surface of a printed circuit board.
  41. Thompson Patrick F. ; Williams William M. ; Lindsey Scott E. ; Vasquez Barbara, Semiconductor wafer contact system and method for contacting a semiconductor wafer.
  42. Smith Kenneth R. (Plano TX), Singulated bare die tester and method of performing forced temperature electrical tests and burn-in.
  43. Spinner Howard D., Smart IC-test receptacle having holes adapted for mounting capacitors arranged adjacent to pin positions.
  44. Dozier ; II Thomas H. ; Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Sockets for electronic components and methods of connecting to electronic components.
  45. Chao Clinton C. (51 Waterside Cir. Redwood City CA 94065) Harper Timothy V. (11260 West Hickory Hill Ct. Boise ID 83704) Wynbeek John C. (10471 Pharlap Dr. Cupertino CA 95014) Schneider Eric S. (3276, Spacing control in electronic device assemblies.
  46. Reymond Welles K. (Waterbury CT), Spring biased tapered contact elements for electrical connectors and integrated circuit packages.
  47. White William J. (Chelmsford MA) Ortolf James M. (Acton MA), Spring finger interconnect for IC chip carrier.
  48. Gore John G. (Sorrento FL), Surface mounting stress relief device and method.
  49. Hembree David R. ; Akram Salman ; Farnworth Warren M. ; Wark James M., Temporary package, method and system for testing semiconductor dice having backside electrodes.
  50. Kade James H. (Plainville MA), Test fixture with diaphragm board with one or more internal grounded layers.
  51. Matrone John L. (Guilderland NY), Universal test fixture employing interchangeable wired personalizers.

이 특허를 인용한 특허 (2)

  1. Do, Trent K., Surface connector with silicone spring member.
  2. Wagman, Daniel C.; Jol, Eric S.; Do, Trent K., Surface connector with silicone spring member.
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