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Integrated connection arrangements 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
  • H01L-029/40
  • H01L-021/4763
  • H01L-021/02
출원번호 UP-0350518 (2006-02-09)
등록번호 US-7619309 (2009-11-27)
우선권정보 DE-103 37 569(2003-08-14)
발명자 / 주소
  • Drexl, Stefan
  • Goebel, Thomas
  • Helneder, Johann
  • Hommel, Martina
  • Klein, Wolfgang
  • Kôrner, Heinrich
  • Mitchell, Andrea
  • Schwerd, Markus
  • Seck, Martin
출원인 / 주소
  • Infineon Technologies AG
대리인 / 주소
    Brinks Hofer Gilson & Lione
인용정보 피인용 횟수 : 40  인용 특허 : 22

초록

A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure a

대표청구항

The invention claimed is: 1. An integrated circuit connection arrangement, comprising: an electrically conductive outer conductive structure being arranged at least partly in a cutout of an electrically insulating insulation layer, the outer conductive structure having at least one edge region adjo

이 특허에 인용된 특허 (22)

  1. Ting Chiu H. (Saratoga CA) Paunovic Milan (Port Washington NY), Electroless deposition for IC fabrication.
  2. Yoon, Jung-Lim; Ahn, Jong-Hyon; Lee, Chang-Hun, Flip chip type semiconductor device and method of fabricating the same.
  3. Scheucher,Heimo, Integrated circuit with at least one bump.
  4. Yoshikawa Kazuhiko,JPX ; Owashi Hitoaki,JPX ; Hayakawa Hiroyuki,JPX ; Otsubo Tadasu,JPX ; Hosokawa Kyoichi,JPX, Interactive chargeable communication system with billing system therefor.
  5. Pozder, Scott K.; Kobayashi, Thomas S., Method for forming a semiconductor device having a mechanically robust pad interface.
  6. Elenius Peter ; Hollack Harry, Method for forming chip scale package.
  7. Suzuki Masayuki,JPX ; Nishihara Shinji,JPX ; Sahara Masashi,JPX ; Ishida Shinichi,JPX ; Abe Hiromi,JPX ; Tohda Sonoko,JPX ; Uchiyama Hiroyuki,JPX ; Tsugane Hideaki,JPX ; Yoshiura Yoshiaki,JPX, Method for making semiconductor integrated circuit device having interconnection structure using tungsten film.
  8. Robl, Werner; Goebel, Thomas; Brintzinger, Axel Christoph; Friese, Gerald, Method of eliminating back-end rerouting in ball grid array packaging.
  9. Burrell,Lloyd G.; Davis,Charles R.; Goldblatt,Ronald D.; Landers,William F.; Mehta,Sanjay C., Method of fabricating a wire bond pad with Ni/Au metallization.
  10. Stuart E. Greer, Method of forming copper interconnection utilizing aluminum capping film.
  11. Charlie Han TW; Kai-Kuang Ho TW, Pad design.
  12. Flynn Todd M. ; Argento Christopher W. ; Larsen Larry J., Process for forming an electrical device.
  13. Tsutsui,Yutaka; Okada,Norio, Semiconductor device.
  14. Mehul D. Shroff ; Philip G. Grigg, Semiconductor device and method of formation.
  15. Toyosawa, Kenji; Ono, Atsushi; Chikawa, Yasunori; Sakaguchi, Nobuhisa; Nakamura, Nakae; Nakata, Yukinori, Semiconductor device having active element connected to an electrode metal pad via a barrier metal layer and interlayer insulating film.
  16. Kariyazono Hiroshi (Tokyo JPX) Honna Katsu (Kawasaki JPX), Semiconductor device with a MOS structure and a manufacturing method thereof.
  17. Oda,Noriaki, Semiconductor device with bonding pad support structure.
  18. Matsuki Hirohisa,JPX ; Kado Kenichi,JPX ; Watanabe Eiji,JPX ; Imamura Kazuyuki,JPX ; Yurino Takahiro,JPX, Semiconductor device with pad structure.
  19. Burrell, Lloyd G.; Kemerer, Douglas; Nye, III, Henry A.; Barth, Hans-Joachim; Crabbe, Emmanuel F.; Anderson, David; Chan, Joseph, Support structures for wirebond regions of contact pads over low modulus materials.
  20. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Motsiff, William T., Thinning of fuse passivation after C4 formation.
  21. Fang, Jen-Kuang, Wafer level chip-scale package.
  22. Matsunaga, Noriaki; Usui, Takamasa; Ito, Sachiyo, Wiring structure of semiconductor device.

이 특허를 인용한 특허 (40)

  1. Rathburn, James, Area array semiconductor device package interconnect structure with optional package-to-package or flexible circuit to package connection.
  2. Rathburn, James, Bumped semiconductor wafer or die level electrical interconnect.
  3. Rathburn, James, Compliant printed circuit area array semiconductor device package.
  4. Rathburn, James, Compliant printed circuit semiconductor package.
  5. Rathburn, James, Compliant printed circuit semiconductor tester interface.
  6. Rathburn, James, Compliant printed circuit socket diagnostic tool.
  7. Rathburn, James, Compliant printed circuit wafer level semiconductor package.
  8. Rathburn, James, Compliant printed circuit wafer probe diagnostic tool.
  9. Rathburn, James, Compliant printed flexible circuit.
  10. Rathburn, James, Compliant wafer level probe assembly.
  11. Rathburn, James, Composite polymer-metal electrical contacts.
  12. Rathburn, James, Copper pillar full metal via electrical circuit structure.
  13. Rathburn, Jim, Copper pillar full metal via electrical circuit structure.
  14. Rathburn, James, Electrical connector insulator housing.
  15. Rathburn, James, Electrical interconnect IC device socket.
  16. Rathburn, James, Electrical interconnect IC device socket.
  17. Rathburn, James, Fusion bonded liquid crystal polymer circuit structure.
  18. Rathburn, James, High performance electrical circuit structure.
  19. Rathburn, James, High performance surface mount electrical interconnect.
  20. Rathburn, James, High performance surface mount electrical interconnect.
  21. Rathburn, James, High performance surface mount electrical interconnect.
  22. Rathburn, James, High speed circuit assembly with integral terminal and mating bias loading electrical connector assembly.
  23. Rathburn, James, Hybrid printed circuit assembly with low density main core and embedded high density circuit regions.
  24. Rathburn, James J., Low profile electrical interconnect with fusion bonded contact retention and solder wick reduction.
  25. Rathburn, James J., Mechanical contact retention within an electrical connector.
  26. Rathburn, James, Metalized pad to electrical contact interface.
  27. Rathburn, James, Method of forming a semiconductor socket.
  28. Rathburn, James, Method of making a compliant printed circuit peripheral lead semiconductor package.
  29. Rathburn, James, Method of making a compliant printed circuit peripheral lead semiconductor test socket.
  30. Rathburn, James J., Method of making an electrical connector having electrodeposited terminals.
  31. Rathburn, Jim, Method of making an electronic interconnect.
  32. Rathburn, James, Performance enhanced semiconductor socket.
  33. Rathburn, James, Resilient conductive electrical interconnect.
  34. Rathburn, Jim, Selective metalization of electrical connector or socket housing.
  35. Rathburn, James, Semiconductor device package adapter.
  36. Akram, Salman; Wark, James M.; Hiatt, William Mark, Semiconductor devices comprising nickel- and copper-containing interconnects.
  37. Rathburn, James, Semiconductor die terminal.
  38. Rathburn, James, Semiconductor socket with direct selective metalization.
  39. Rathburn, James, Simulated wirebond semiconductor package.
  40. Rathburn, James, Singulated semiconductor device separable electrical interconnect.
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