초록 ▼

A system, apparatus and a method for routing data over fewer switches and interconnections among reconfigurable logic elements, and for adapting routing resources to dynamically perform complex bit-level permutations, such as shifting and bit reversal operations. In one embodiment, an exemplary silo

A system, apparatus and a method for routing data over fewer switches and interconnections among reconfigurable logic elements, and for adapting routing resources to dynamically perform complex bit-level permutations, such as shifting and bit reversal operations. In one embodiment, an exemplary silo routing circuit is formed upon a semiconductor substrate and routes data among a number of reconfigurable computational elements. The silo routing circuit comprises a plurality of input terminals and a plurality of output terminals. Further, the silo routing circuit includes a multi-stage interconnection network ("MIN") of switches configurable to form data paths from any input terminal to any output terminal.

대표청구항 ▼

The invention claimed is: 1. A reconfigurable logic array for implementing a reconfigurable data-path processor formed on a semiconductor substrate, the reconfigurable logic array comprising: a plurality of reconfigurable computational elements; and a plurality of silo routers, the plurality of sil

The invention claimed is: 1. A reconfigurable logic array for implementing a reconfigurable data-path processor formed on a semiconductor substrate, the reconfigurable logic array comprising: a plurality of reconfigurable computational elements; and a plurality of silo routers, the plurality of silo routers including a silo router that includes a plurality of silo router circuits located between at least a first reconfigurable computational element from the plurality of reconfigurable computation elements and a second reconfigurable computational element from the plurality of reconfigurable computation elements, said plurality of silo routers configured to perform bit permutations on data being transmitted from said first reconfigurable computational element to said second reconfigurable computational element, the plurality of silo routers including the silo router having: a plurality of input terminals and a plurality of output terminals, said plurality of output terminals including a first output terminal and a second output terminal; a plurality of switches; and a plurality of configuration data terminals configured to select a subset of the plurality of switches such that the subset of the plurality of switches defines at least a portion of a data path between at least one of the plurality of input terminals and at least one of the plurality of output terminals, said second output terminal being separated from said first output terminal by a distance defined based on a bit vector applied to a subset of the plurality of configuration data terminals, said distance being a displacement in a quantity of output terminals from said first output terminal, the plurality of switches having a switch in a first stage of switches, the switch in the first stage of switches being at least a binary switch having at least a first input terminal configured to receive data from a first switch in a second stage of switches without the data being transmitted through another of the plurality of switches, the switch in the first stage switches having a second input terminal configured to receive data from a second switch in the second stage of switches without the data being transmitted through another of the plurality of switches, the second switch in the second stage of switches being in a row of switches located 2M-k rows from a row of switches including the switch in the first stage of switches, M being a number representing a total number of stages of switches defined by the plurality of switches and k being a number representing an order of the first stage of switches within the total number of stages of switches. 2. The reconfigurable logic array of claim 1, wherein said plurality of silo routers are further configured to route data from said first reconfigurable computational element to said second reconfigurable computational element substantially orthogonal to data flowing through said first and said second reconfigurable computational elements. 3. The reconfigurable logic array of claim 2, further comprising a plurality of dynamic switches each configurable to either statically route data or dynamically route data from said first reconfigurable computational element to said second reconfigurable computational element. 4. The reconfigurable logic array of claim 3, wherein said plurality of dynamic switches further comprises a plurality of dynamic configuration elements including: a plurality of embedded storage elements for storing configuration data configured to trigger at least one of said plurality of silo routers to statically route data from said first reconfigurable computational element to said second reconfigurable computational element; and a plurality of dynamic control selector gates configured to override said configuration data such that data is dynamically routed through said plurality of dynamic switches. 5. The reconfigurable logic array of claim 1, wherein said plurality of reconfigurable computational elements constitute a number of arithmetic logic unit ("ALU") blocks and said plurality of silo routers constitute a number of transitive routers. 6. The reconfigurable logic array of claim 1, wherein said bit permutations include one or more of bit reversal operations, bit swapping operations, bit rotation operations and bit shifting operations. 7. The reconfigurable logic array of claim 1, wherein at least one of said silo routers includes a one-sided silo router circuit configured to perform either a shift right operation or a shift left operation. 8. The reconfigurable logic array of claim 1, wherein the first stage of switches and the second stage of switches are logically disposed between a third stage of switches from the plurality of switches and a fourth stage of switches from the plurality of switches. 9. The reconfigurable logic array of claim 1, wherein M is greater than three. 10. The reconfigurable logic array of claim 1, wherein the first stage of switches is adjacent to the second stage of switches.