[미국특허]
Systems for testing and packaging integrated circuits
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01R-012/00
H05K-001/00
출원번호
UP-0781172
(2007-07-20)
등록번호
US-7621761
(2009-12-02)
발명자
/ 주소
Mok, Sammy
Chong, Fu Chiung
Milter, Roman
출원인 / 주소
NanoNexus, Inc.
대리인 / 주소
Glenn, Michael A.
인용정보
피인용 횟수 :
55인용 특허 :
298
초록▼
Several embodiments of stress metal springs are disclosed, which typically comprise a plurality of stress metal layers that are established on a substrate, which are then controllably patterned and partially released from the substrate. An effective rotation angle is typically created in the formed
Several embodiments of stress metal springs are disclosed, which typically comprise a plurality of stress metal layers that are established on a substrate, which are then controllably patterned and partially released from the substrate. An effective rotation angle is typically created in the formed stress metal springs, defining a looped spring structure. The formed springs provide high pitch compliant electrical contacts for a wide variety of interconnection systems, including chip scale semiconductor packages, high density interposer connectors, and probe contactors. Several embodiments of massively parallel interface integrated circuit test assemblies are also disclosed, comprising one or more substrates having stress metal spring contacts, to establish connections between one or more separated integrated circuits on a compliant wafer carrier.
대표청구항▼
The invention claimed is: 1. A contactor, comprising: at least one stress metal spring formed on a surface of a substrate, the stress metal spring having an anchor portion attached to the substrate surface and a free portion extending away from the substrate surface, the stress metal spring compris
The invention claimed is: 1. A contactor, comprising: at least one stress metal spring formed on a surface of a substrate, the stress metal spring having an anchor portion attached to the substrate surface and a free portion extending away from the substrate surface, the stress metal spring comprising a plurality of layers that together impart an inherent level of stress to the spring which effects rotation of the free portion of the stress metal spring from the substrate surface by an effective rotation angle; and at least one plated metal layer substantially covering the stress metal spring. 2. The contactor of claim 1, wherein the at least one plated metal layer comprises any of nickel, an alloy of nickel which is selected from the group comprising nickel iron, nickel cobalt, nickel cobalt iron, nickel molly, nickel tungsten, nickel iron tungsten, nickel cobalt tungsten, nickel rhodium, nickel cobalt manganese, nickel iron rhodium, nickel iron manganese, palladium, an alloy of palladium, palladium cobalt, gold, an alloy of gold, silver, rhodium, cobalt, an alloy of cobalt, tin, an alloy of tin, copper, an alloy of copper, and lead containing or lead free solder materials. 3. The contactor of claim 1, wherein the at least one plated metal layer is applied with any of electroplating, electroless plating, sputtering and evaporation. 4. The contactor of claim 1, wherein the at least one plated metal layer provides any of increased mechanical strength, reduced electrical resistance, increased resistance to mechanical wear and reduced debris pickup. 5. The contactor of claim 1, wherein the free portion of the at least one stress metal spring extends from the anchor portion to define a tip, and wherein the at least one plated metal layer envelopes at least a portion of the free portion of the at least one stress metal spring extending from the tip toward the anchor portion. 6. The contactor of claim 1, wherein the at least one stress metal spring provides an electrical connection to any of a printed wiring board, an integrated circuit, a chip scale package, and a solder ball. 7. The contactor of claim 1, wherein the at least one stress metal spring comprises a plurality the stress metal springs defining an array for providing any of tight pitch, vertical compliance, and planarity compliance. 8. The contactor of claim 1, wherein the contactor comprises any of an interposer, a separable connector, and an interface assembly. 9. The contactor of claim 1, wherein the substrate comprises any of an integrated circuit package, an integrated circuit device, and a printed circuit board. 10. A process for forming a contactor, comprising the steps of: forming at least one stress metal spring on a surface of a substrate which, upon release from said surface, has an anchor portion and a free portion, the stress metal spring comprising a plurality of layers that together impart an inherent level of stress to the spring; and releasing the free portion of the stress metal spring from the substrate surface, wherein the free portion of the stress metal spring rotates away from the substrate surface by an effective rotation angle due to the inherent level of stress; and covering the stress metal spring with at least one plated metal layer. 11. The process of claim 10, wherein the at least one plated metal layer comprises any of nickel, an alloy of nickel which is selected from the group comprising nickel iron, nickel cobalt, nickel cobalt iron, nickel molly, nickel tungsten, nickel iron tungsten, nickel cobalt tungsten, nickel rhodium, nickel cobalt manganese, nickel iron rhodium, nickel iron manganese, palladium, an alloy of palladium, palladium cobalt, gold, an alloy of gold, silver, rhodium, cobalt, an alloy of cobalt, tin, an alloy of tin, copper, an alloy of copper, and lead containing or lead free solder materials. 12. The process of claim 10, wherein the covering step comprises any of electroplating, electroless plating, sputtering, and evaporation. 13. The process of claim 10, wherein the at least one plated metal layer provides any of increased mechanical strength, reduced electrical resistance, increased resistance to mechanical wear and reduced debris pickup. 14. The process of claim 10, wherein the free portion of the at least one stress metal spring extends from the anchor portion to define a tip, and wherein the at least one plated metal layer envelopes at least a portion of the free portion of the at least one stress metal spring extending from the tip toward the anchor portion. 15. The process of claim 10, further comprising the step of: establishing an electrical connection between the at least one stress metal spring and any of a printed wiring board, an integrated circuit, a chip scale package, and a solder ball. 16. The process of claim 10, wherein the at least one stress metal spring comprises a plurality the stress metal springs defining an array for providing any of tight pitch, vertical compliance, and planarity compliance. 17. The process of claim 10, wherein the substrate and the at least one stress metal spring comprises any of an interposer, a separable connector, and an interface assembly. 18. The process of claim 10, wherein the substrate comprises any of an integrated circuit package, an integrated circuit device, and a printed circuit board.
Little Michael J. (Woodland Hills CA) Grinberg Jan (Los Angeles CA) Garvin Hugh L. (Malibu CA), 3-D integrated circuit assembly employing discrete chips.
Thomas L. Ritzdorf ; Steve L. Eudy ; Gregory J. Wilson ; Paul R. McHugh, Apparatus and method for electrochemical processing of a microelectronic workpiece, capable of modifying processing based on metrology.
Buol Douglas A. (Dallas TX) Mize Dean N. (Garland TX) Pattschull John W. (Garland TX) Wallace Robert M. (Dallas TX), Apparatus for testing integrated circuits.
Harra David J. (Santa Cruz CA) Turner Frederick T. (Sunnyvale CA) Hutchinson Martin A. (Santa Clara CA), Blocking shield and method for contouring the thickness of sputter coated layers.
Hottenrott Hans G. (Wappingers Falls NY) Hodge Philo B. (Roxbury CT) Cochran Thomas J. (La Grangeville NY), Buckling beam twist probe contactor assembly with spring biased stripper plate.
Panicker Ramachandra M. P. (Camarillo CA) Agarwal Anil K. (Poway CA), Ceramic substrate with metal filled via holes for hybrid microcircuits and method of making the same.
DiStefano Thomas H. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan ; Sweis Jason ; Union Laurie ; Gibson David, Connection components with frangible leads and bus.
Mok, Sammy; Chong, Fu Chiung; Swiatowiec, Frank John; Lahiri, Syamal Kumar; Haemer, Joseph Michael, Construction structures and manufacturing processes for probe card assemblies and packages having wafer level springs.
Khandros Igor Y. ; Eldridge Benjamin N. ; Mathieu Gaetan L. ; Dozier Thomas H. ; Smith William D., Contact carriers (tiles) for populating larger substrates with spring contacts.
Khandros, Igor Y.; Eldridge, Benjamin N.; Mathieu, Gaetan L.; Dozier, Thomas H.; Smith, William D., Contact carriers (tiles) for populating larger substrates with spring contacts.
Long Tom (Portland OR) Sabri Mohamed (Beaverton OR) Saunders J. Lynn (Hillsboro OR), Contact device for making connection to an electronic circuit device.
Bohlen Harald (Boeblingen DEX) Kas Gerhard (Moetzingen DEX) Greschner Johann (Pliezhausen DEX) Keyser Joachim H. (Wildberg DEX) Klcke Werner (Boeblingen DEX), Contact device for releasably connecting electrical components.
Khandros Igor Y. ; Mathieu Gaetar L., Contact structure device for interconnections, interposer, semiconductor assembly and package using the same and method.
Buechele Alvin W. (Lagrangeville NY) Cochran Thomas J. (Lagrangeville NY) Hodge Philo B. (Roxbury CT), Contactor and probe assembly for electrical test apparatus.
Vaynkof Yakov F. (Woodland Hills CA) Zimmermann Karl F. (Agoura CA) Shorter Jerry W. (Camarillo CA) Bond Joseph K. (Newbury Park CA), Contactor with elastomer encapsulated probes.
Sarma Dwadasi H. R. (West Lafayette IN) Palanisamy Ponnusamy (Kokomo IN) Hearn John A. (Kokomo IN) Schwarz Dwight L. (Kokomo IN), Controlled adhesion conductor.
Forster John C. ; Stimson Bradley O. ; Xu Zheng, Darkspace shield for improved RF transmission in inductively coupled plasma sources for sputter deposition.
Koby L. Duckworth ; Miguel L. Islas ; Timothy Eric Gilliam, Electrical test probe card having a removable probe head assembly with alignment features and a method for aligning the probe head assembly to the probe card.
Eldridge Benjamin N. ; Khandros Igor Y. ; Mathieu Gaetan L. ; Pedersen David V., Electronic components with terminals and spring contact elements extending from areas which are remote from the terminals.
Prinz Fritz B. (5801 Northumberland St. Pittsburgh PA 15217) Weiss Lee E. (6558 Darlington Rd. Pittsburgh PA 15217) Siewiorek Daniel P. (1259 Bellerock St. Pittsburgh PA 15217), Electronic packages and smart structures formed by thermal spray deposition.
McNair Michael P. ; Redondo Louis H. ; Dimitropoulos Nicholas M. ; Meirhofer Donald A., Electronic test probe interface assembly and method of manufacture.
Lopergolo Emanuele Frank ; Goldmann Lewis Sigmund ; Sullivan Joseph Michael ; Tompkins ; Jr. Charles Russell, High density electrical interconnect apparatus and method.
Farquhar Donald Seton ; Jimarez Lisa Jeanine ; Klodowski Michael Joseph ; Zimmerman Jeffrey Alan, Integrated circuit chip carrier assembly comprising a stiffener attached to a dielectric substrate.
Bregman Mark F. (Ridgefield CT) Hoffman Paul R. (Santa Clara CA) Ledermann Peter G. (Ossining NY) Moskowitz Paul A. (Yorktown Heights NY) Pollak Roger A. (Pleasantville NY) Reiley Timothy C. (Los Gat, Integrated circuit testing system having a cantilevered contact lead probe pattern mounted on a flexible tape for interc.
Gopalraja Praburam ; Fu Jianming ; Chen Fusen ; Dixit Girish ; Xu Zheng ; Athreya Sankaram ; Wang Wei D. ; Sinha Ashok K., Integrated process for copper via filling using a magnetron and target producing highly energetic ions.
Perry Charles H. (Poughkeepsie NY) Bauer Tibor L. (Hopewell Junction NY) Long David C. (Wappingers Falls NY) Pickering Bruce C. (Wappingers Falls NY) Vittori Pierre C. (Cold Spring NY), Interface card for a probe card assembly.
Das Gobina ; Gaschke Paul Mathew ; Hegde Suryanarayan G. ; LaForce Mark Raymond ; McHerron Dale Curtis ; Perry Charles Hampton ; Taber ; Jr. Frederick L., Large area multiple-chip probe assembly and method of making the same.
Cao Wei ; Ward James ; Tregoning Mike ; Yang Xingbo, Magnetic recording media having CrTiX underlayers to reduce circumferential/radial anisotropy and methods for their production.
Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Making discrete power connections to a space transformer of a probe card assembly.
Eldridge Benjamin N. ; Khandros Igor Y. ; Mathieu Gaetan L., Method and apparatus for applying a layer of flowable coating material to a surface of an electronic component.
Claude Montcalm ; James Allen Folta ; Swie-In Tan ; Ira Reiss, Method and system using power modulation for maskless vapor deposition of spatially graded thin film and multilayer coatings with atomic-level precision and accuracy.
Elder Richard A. (Dallas TX) Wilson Arthur M. (Dallas TX) Bagen Susan V. (Dallas TX) Miller Juanita G. (Richardson TX), Method for fabrication of probe card for testing of semiconductor devices.
Farnworth Warren M. (Nampa ID) Grief Malcolm (Boise ID) Sandhu Gurtej S. (Boise ID), Method for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor cir.
King Jerrold L. (Boise ID) Brooks Jerry M. (Caldwell ID) Farnworth Warren M. (Nampa ID) McGill George P. (Boise ID), Method for testing, burning-in, and manufacturing wafer scale integrated circuits and a packaged wafer assembly produced.
Woith Blake F. (Orange CA) Pasiecznik ; Jr. John (Malibu CA) Crumly William R. (Anaheim CA) Betz Robert K. (Long Beach CA), Method of making a cast elastomer/membrane test probe assembly.
Chen Jimmy Kuo-Wei ; Eldridge Benjamin N. ; Dozier Thomas H. ; Yeh Junjye J. ; Herman Gayle J., Method of making a product with improved material properties by moderate heat-treatment of a metal incorporating a dilute additive.
Yasunaga, Masatoshi; Kimura, Michitaka; Yamada, Satoshi, Method of manufacturing a packaged semiconductor device, and a semiconductor device manufactured thereby.
Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y ; Mathieu Gaetan L., Method of modifying the thickness of a plating on a member by creating a temperature gradient on the member, applications for employing such a method, and structures resulting from such a method.
Spierings Gijsbertus A.C.M.,NLX ; Heijboer Willem L.C.M.,NLX ; Remeeus Leo O.,NLX, Method of photolithographically metallizing at least the inside of holes arranged in accordance with a pattern in a plat.
Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of temporarily, then permanently, connecting to a semiconductor device.
Mei, Ping; Sun, Decai; Street, Robert A., Microelectromechanical system based sensors, sensor arrays, sensing systems, sensing methods and methods of fabrication.
Bellaar Pieter H.,NLX ; DiStefano Thomas H. ; Fjelstad Joseph ; Pickett Christopher M. ; Smith John W., Microelectronic component with rigid interposer.
DiStefano Thomas H. (Bronxville NY) Ehrenberg Scott G. (Fishkill NY) Khandros Igor Y. (Peekskill NY), Multi-layer circuit structures, methods of making same and components for use therein.
Erb Uwe (Glenburnie CAX) El-Sherik Abdelmounam M. (Kingston CAX) Cheung Cedric K. S. (Kingston CAX) Aus Martin J. (Kingston CAX), Nanocrystalline metals.
Smith Donald L. ; Thornton Robert L. ; Chua Christopher L. ; Fork David K., Photolithographically patterned spring contact and apparatus and methods for electrically contacting devices.
Chua, Christopher L.; Lemmi, Francesco; Van Schuylenbergh, Koenraad F.; Lu, Jeng Ping; Fork, David K.; Peeters, Eric; Sun, Decai; Smith, Donald L.; Romano, Linda T., Photolithographically-patterned out-of-plane coil structures and method of making.
Christopher L. Chua ; Eric Peeters ; Koenraad F. Van Schuylenbergh ; Donald L. Smith, Photolithographically-patterned variable capacitor structures and method of making.
Tony P. Chiang ; Yu D. Cong ; Peijun Ding ; Jianming Fu ; Howard H. Tang ; Anish Tolia, Plasma reactor and shields generating self-ionized plasma for sputtering.
Perry Charles H. (Poughkeepsie NY) Bauer Tibor L. (Hopewell Junction NY) Long David C. (Wappingers Falls NY) Pickering Bruce C. (Wappingers Falls NY) Vittori Pierre C. (Cold Spring NY), Probe card assembly.
Perry Charles H. (Poughkeepsie NY) Bauer Tibor L. (Hopewell Junction NY) Long David C. (Wappingers Falls NY) Pickering Bruce C. (Wappingers Falls NY) Vittori Pierre C. (Cold Spring NY), Probe card assembly having a ceramic probe card.
Hembree David R. ; Farnworth Warren M. ; Akram Salman ; Wood Alan G. ; Doherty C. Patrick ; Krivy Andrew J., Probe card for semiconductor wafers and method and system for testing wafers.
Okubo Kazumasa (Kanagawa JPX) Okubo Masao (Nishinomiya JPX) Yoshimitsu Yasuro (Takatsuki JPX) Sugaya Kiyoshi (Amagasaki JPX), Probe card in which contact pressure and relative position of each probe end are correctly maintained.
Nulty, James E.; Brophy, Brenor L.; McCleary, Thomas A.; Jin, Bo; Gu, Qi; Rodgers, Thurman J.; Torode, John O., Probe card with an adapter layer for testing integrated circuits.
Lee Si-Hyoung,KRX ; Park Seung-Hwan,KRX ; Yang Kyoung-Ho,KRX ; Lee Gun-Won,KRX, Probe control method for leveling probe pins for a probe test sequence.
Lefebvre Paul M. ; Seeser James W. ; Seddon Richard Ian ; Scobey Michael A. ; Manley Barry W., Process for depositing optical thin films on both planar and non-planar substrates.
Suppelsa Anthony B. (Coral Springs FL) Mullen ; III William B. (Boca Raton FL) Urbish Glenn F. (Coral Springs FL), Selectively releasing conductive runner and substrate assembly.
Banerji Kingshuk (Plantation FL) Suppelsa Anthony B. (Coral Springs FL) Mullen ; III. William B. (Boca Raton FL), Selectively releasing conductive runner and substrate assembly having non-planar areas.
Khandros Igor Y. (Peekskill NY) DiStefano Thomas H. (Bronxville NY), Semiconductor chip assemblies with face-up mounting and rear-surface connection to substrate.
Leas James M. (South Burlington VT) Koss Robert W. (Burlington VT) Walker George F. (New York NY) Perry Charles H. (Poughkeepsie NY) Van Horn Jody J. (Underhill VT), Semiconductor wafer test and burn-in.
Blackwell Kim J. (Owego NY) White ; Jr. Russell T. (Binghamton NY) Wilson James W. (Vestal NY), Shield for improved magnetron sputter deposition into surface recesses.
Dozier ; II Thomas H. ; Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L. ; Pedersen David V. ; Stadt Michael A., Sockets for "springed" semiconductor devices.
Dozier, II, Thomas H.; Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L.; Pedersen, David V.; Stadt, Michael A., Sockets for "springed" semiconductor devices.
Dozier ; II Thomas H. ; Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Sockets for electronic components and methods of connecting to electronic components.
Harra David J. (Santa Cruz CA) Turner Frederick T. (Sunnyvale CA) Hutchinson Martin A. (Santa Clara CA), Sputter system incorporating an improved blocking shield for contouring the thickness of sputter coated layers.
Evans Arthur (Brookfield Center CT) Baker Joseph R. (New Milford CT) Rising Robert P. (Trumbull CT), Test probe assembly for testing integrated circuit devices.
Beaman Brian Samuel ; Fogel Keith Edward ; Lauro Paul Alfred ; Norcott Maurice Heathcote ; Shih Da-Yuan ; Walker George Frederick, Test probe for high density integrated circuits, methods of fabrication thereof and methods of use thereof.
Beaman Brian S. (Hyde Park NY) Fogel Keith E. (Bardonia NY) Lauro Paul A. (Nanuet NY) Norcott Maurice H. (Valley Cottage NY) Shih Da-Yuan (Poughkeepsie NY) Walker George F. (New York NY), Test probe having elongated conductor embedded in an elostomeric material which is mounted on a space transformer.
Farnworth Warren M. (Nampa ID) Grief Malcolm (Boise ID) Sandhu Gurtej S. (Boise ID), Testing apparatus for engaging electrically conductive test pads on a semiconductor substrate having integrated circuitr.
Kamerling Marc A. (Santa Rosa CA) Beauchamp William T. (Santa Rosa CA) Klinger Robert E. (Rohnert Park CA) Lehan John P. (Calistoga CA), Thin film coating and method.
Scobey Michael A. (Aliso Viejo CA) Bryn Stanley L. (Chelmsford MA), Very high vacuum magnetron sputtering method and apparatus for precision optical coatings.
Atkins Glen G. (Boise ID) Cohen Michael S. (Boise ID) Mauritz Karl H. (Eagle ID) Shaffer James M. (Boise ID 4), Wafer scale burn-in apparatus and process.
Rathburn, James, Area array semiconductor device package interconnect structure with optional package-to-package or flexible circuit to package connection.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.