Input/output controller node in an adaptable computing environment
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-003/00
G06F-013/00
출원번호
UP-0719409
(2003-11-22)
등록번호
US-7624204
(2009-12-02)
발명자
/ 주소
Furtek, Frederick Curtis
Master, Paul L.
Plunkett, Robert Thomas
출원인 / 주소
NVIDIA Corporation
대리인 / 주소
Patterson & Sheridan, LLP
인용정보
피인용 횟수 :
0인용 특허 :
62
초록▼
A reconfigurable input/output controller (IOC) allows an adaptive computing engine (ACE) to communicate with external devices. The external devices can comprise a separate system on chip (SOC) or can be other devices or resources such as audio/visual output devices, memory, network or other communic
A reconfigurable input/output controller (IOC) allows an adaptive computing engine (ACE) to communicate with external devices. The external devices can comprise a separate system on chip (SOC) or can be other devices or resources such as audio/visual output devices, memory, network or other communications, etc. The IOC allows different modes of transfer and performs necessary translation of input and output commands. In one embodiment, the IOC adheres to standard messaging and communication protocol used by other nodes in the ACE. This approach allows a uniform approach to the ACE design and provides advantages in scalability and adaptability of the ACE system. One feature of the invention provides a physical link adapter for accommodating different external communication types such as, RS231, optical, Firewire, universal synchronous bus (USB), etc. The physical link adapter uses a reconfigurable finite state machine, selectable couplings and a bus switch to allow connection of different communication types' signals to a common ACE component such as to an IOC.
대표청구항▼
What is claimed is: 1. An adaptive computing engine, comprising: a programmable interconnection network; a plurality of nodes, wherein each node included in the plurality of nodes has a fixed and different architecture that corresponds to a particular algorithmic function, and each node is coupled
What is claimed is: 1. An adaptive computing engine, comprising: a programmable interconnection network; a plurality of nodes, wherein each node included in the plurality of nodes has a fixed and different architecture that corresponds to a particular algorithmic function, and each node is coupled to one or more other nodes in the plurality of nodes via the programmable interconnection network; a reconfigurable input/output (I/O) controller coupled to a first node in the plurality of nodes via the programmable interconnection network, the reconfigurable I/O controller including: at least one input coupled to the programmable interconnection network for receiving a point-to-point transfer instruction from the first node, and at least one output for providing a translated point-to-point transfer instruction to an external device; and a physical link adapter coupled to the reconfigurable I/O controller, wherein the physical link adapter is coupled to coupling circuitry and includes a reconfigurable finite-state machine configured to control the coupling circuitry to selectively connect a signal from a physical connector. 2. The adaptive computing engine of claim 1, wherein the translated point-to-point transfer instruction provides translation of a port number in the adaptive computing engine to the external device. 3. The adaptive computing engine of claim 1, wherein the translated point-to-point transfer instruction provides translation of an address associated with the adaptive computing engine to an address associated with the external device. 4. The adaptive computing engine of claim 1, wherein the reconfigurable I/O controller further includes Peek/Poke service circuitry. 5. The adaptive computing engine of claim 1, wherein the reconfigurable I/O controller further includes memory random access circuitry. 6. The adaptive computing engine of claim 1, wherein the reconfigurable I/O controller further includes direct memory access circuitry. 7. The adaptive computing engine of claim 1, wherein the reconfigurable I/O controller further includes real time input circuitry. 8. The adaptive computing engine of claim 1, wherein the reconfigurable I/O controller further includes a status line coupled to the external device for indicating an availability of services. 9. The adaptive computing engine of claim 1, wherein the programmable interconnection network enables communication among the plurality of nodes and interfaces to reconfigure the adaptive computing engine for a variety of tasks. 10. The adaptive computing engine of claim 1, wherein the reconfigurable I/O controller runs at a clock rate associated with the programmable interconnection network. 11. The adaptive computing engine of claim 1, wherein the external devices include at least one adaptive computing engine, and at least one system on a chip (SOC). 12. The adaptive computing engine of claim 11, wherein the reconfigurable I/O controller further includes status lines coupled to the SOC, the SOC being responsive to the status lines to prioritize multiple external devices. 13. The adaptive computing engine of claim 1, wherein the external device includes at least one of a host computer and a central processing unit. 14. The adaptive computing engine of claim 11, wherein the SOC includes at least one of a storage system, a network access system, or a digital signal processor (DSP).
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (62)
David Lee TW; Cheng-Wang Huang TW, Apparatus and method for serial data communication between plurality of chips in a chip set.
Martin Bryan R. ; Barraclough Keith, Communication interface between remote transmission of both compressed video and other data and data exchange with local peripherals.
Popli Sanjay (Sunnyvale CA) Pickett Scott (Los Gatos CA) Hawley David (Belmont CA) Moni Shankar (Santa Clara CA) Camarota Rafael C. (San Jose CA), Configuration features in a configurable logic array.
Martin Vorbach DE; Robert Munch DE, Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
Wolrich, Gilbert; Bernstein, Debra; Cutter, Daniel; Dolan, Christopher; Adiletta, Matthew J., Mapping requests from a processing unit that uses memory-mapped input-output space.
Bertolet Allan Robert ; Clinton Kim P.N. ; Gould Scott Whitney ; Keyser III Frank Ray ; Reny Timothy Shawn ; Zittritsch Terrance John, Method and system for layout and schematic generation for heterogeneous arrays.
Cooke Laurence H. ; Phillips Christopher E. ; Wong Dale, Method for compiling high level programming languages into an integrated processor with reconfigurable logic.
Vorbach, Martin; Munch, Robert, Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).
Martin Vorbach DE; Robert Munch DE, Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--.
Camarota Rafael C. (San Jose CA) Furtek Frederick C. (Menlo Park CA) Ho Walford W. (Saratoga CA) Browder Edward H. (Saratoga CA), Programmable logic cell and array.
Camarota Rafael C. (San Jose CA) Furtek Frederick C. (Menlo Park CA) Ho Walford W. (Saratoga CA) Browder Edward H. (Saratoga CA), Programmable logic cell and array with bus repeaters.
Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.
Davis Donald J. ; Bennett Toby D. ; Harris Jonathan C. ; Miller Ian D. ; Edwards Stephen G., System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects.
Martin Vorbach DE; Robert Munch DE, UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA-FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAY.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.