Low noise, low power and high bandwidth capacitive feedback trans-impedance amplifier with differential FET input and bipolar emitter follower feedback
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03F-003/16
H03F-003/04
출원번호
UP-0980294
(2007-10-30)
등록번호
US-7626460
(2009-12-16)
발명자
/ 주소
Liu, Kanon
Asbrock, James F.
출원인 / 주소
Raytheon Company
대리인 / 주소
Alkov, Leonard A.
인용정보
피인용 횟수 :
1인용 특허 :
7
초록▼
A differential amplifier topology includes circuitry to create a higher bandwidth output using less current than an existing Capacitive Trans-Impedance Amplifier (CTIA) using an all Field Effect Transistor (FET) circuit design. A bipolar npn emitter follower in the circuit topology provides low outp
A differential amplifier topology includes circuitry to create a higher bandwidth output using less current than an existing Capacitive Trans-Impedance Amplifier (CTIA) using an all Field Effect Transistor (FET) circuit design. A bipolar npn emitter follower in the circuit topology provides low output impedance and some degree of output inductive peaking, and the CTIA differential output is buffered by the bipolar npn emitter follower in the CTIA feedback loop such as the open-loop high voltage gain is maintained without being affected by output loads.
대표청구항▼
What is claimed is: 1. A capacitive trans-impedance amplifier, comprising: first and second input nodes coupled to gate inputs of first and second field effect transistors, respectively; and first and second output nodes, where said first and second output nodes are coupled to emitters of first and
What is claimed is: 1. A capacitive trans-impedance amplifier, comprising: first and second input nodes coupled to gate inputs of first and second field effect transistors, respectively; and first and second output nodes, where said first and second output nodes are coupled to emitters of first and second bipolar transistors, respectively, each of said first and second bipolar transistors being provided in an emitter follower configuration, wherein the emitters of the first and second bipolar transistors are further coupled to the gate inputs of the first and second field effect transistors, respectively. 2. The capacitive transimpedance amplifier of claim 1, further comprising first and second capacitances switchably coupled between said first and second output nodes and said first and second input nodes, respectively, for reducing gain and increasing bandwidth of the capacitive transimpedance amplifier when said first and second capacitances are coupled between said first and second output nodes and said first and second input nodes. 3. The capacitive transimpedance amplifier of claim 2, where the first and second capacitances are selectable for adjusting gain and bandwidth output of the capacitive transimpedance amplifier. 4. The capacitive transimpedance amplifier of claim 1, where one of said input nodes is coupled to a radiation detector, and the other of said input nodes is coupled to a reference voltage. 5. The capacitive transimpedance amplifier of claim 1, embodied in a readout integrated circuit that is hybridized with a focal plane array of radiation detectors. 6. The capacitive transimpedance amplifier of claim 1, wherein the emitters of first and second bipolar transistors are switchably coupled to gates of the first and second field effect transistors, respectively, for pre-setting the output DC bias of the first and second field effect transistors when said emitters of first and second bipolar transistors are coupled to the gates of the first and second field effect transistors, respectively. 7. A readout integrated circuit, comprising an array of capacitive transimpedance amplifiers individual ones of which comprise first and second input nodes coupled to gate inputs of first and second field effect transistors, respectively; and first and second output nodes, where said first and second output nodes are coupled to emitters of first and second bipolar transistors, respectively, each of said first and second bipolar transistors being provided in an emitter follower configuration. 8. The readout integrated circuit as in claim 7, where said individual ones of said capacitive transimpedance amplifiers each further comprise first and second capacitances switchably coupled between said first and second output nodes and said first and second input nodes, respectively, for reducing gain and increasing bandwidth of the capacitive transimpedance amplifier when said first and second capacitances are coupled between said first and second output nodes and said first and second input nodes. 9. The readout integrated circuit as in claim 8, where the first and second capacitances are selectable for adjusting gain and bandwidth output of the capacitive transimpedance amplifier. 10. The readout integrated circuit as in claim 7, where one of said input nodes is coupled to a radiation detector, and the other of said input nodes is coupled to a reference voltage. 11. The readout integrated circuit as in claim 7, further comprising a plurality of switch devices to periodically preset a DC bias potential of the first and second field effect transistors with the emitters of the first and second bipolar transistors. 12. The readout integrated circuit as in claim 7, wherein the emitters of first and second bipolar transistors are switchably coupled to gates of the first and second field effect transistors, respectively, for pre-setting the output DC bias of the first and second field effect transistors when said emitters of first and second bipolar transistors are coupled to the gates of the first and second field effect transistors, respectively. 13. A method, comprising: receiving a signal on a first circuit, comprising a first and second input nodes coupled to gate inputs of first and second field effect transistors, respectively; and amplifying and outputting the received signal on a second circuit, comprising first and second output nodes, where said first and second output nodes are coupled to emitters of first and second bipolar transistors, respectively, each of said first and second bipolar transistors being provided in an emitter follower configuration, wherein the emitters of the first and second bipolar transistors are further coupled to the gate inputs of the first and second field effect transistors, respectively. 14. The method of claim 13, wherein the second circuit further comprises: first and second capacitances switchably coupled between said first and second output nodes and said first and second input nodes, respectively, for reducing gain and increasing bandwidth of the capacitive transimpedance amplifier when said first and second capacitances are coupled between said first and second output nodes and said first and second input nodes, and where the first and second capacitances are selectable for adjusting gain and bandwidth output of the capacitive transimpedance amplifier. 15. The method of claim 13, wherein the first circuit further comprises one of said input nodes is coupled to a radiation detector, and the other of said input nodes is coupled to a reference voltage. 16. The method of claim 13, wherein the first and second circuit is embodied in a readout integrated circuit that is hybridized with a focal plane array of radiation detectors. 17. The method of claim 13, wherein the second circuit wherein the emitters of first and second bipolar transistors are switchably coupled to gates of the first and second field effect transistors, respectively, for pre-setting the output DC bias of the first and second field effect transistors when said emitters of first and second bipolar transistors are coupled to the gates of the first and second field effect transistors, respectively. 18. The method of claim 13, wherein the first and second capacitances are selectable for adjusting gain and bandwidth output of the capacitive transimpedance amplifier. 19. A capacitive trans-impedance amplifier, comprising: means for receiving a signal on a first circuit, comprising a first and second input nodes coupled to gate inputs of first and second field effect transistors, respectively; and means for amplifying and outputting the received signal on a second circuit, comprising first and second output nodes, where said first and second output nodes are coupled to emitters of first and second bipolar transistors, respectively, each of said first and second bipolar transistors being provided in an emitter follower configuration, wherein the emitters of the first and second bipolar transistors are further coupled to the gate inputs of the first and second field effect transistors, respectively. 20. The capacitive trans-impedance amplifier of claim 19, wherein the means for receiving a signal on the first circuit comprises a receiver circuit; and the means for amplifying and outputting the received signal on the second circuit comprises an amplifier and feedback circuit.
Morse Arthur L. (Hawthorne CA) Gaalema Steve D. (Encinitas CA) Keimel Ingrid M. (Fountain Valley CA) Hewitt Mary J. (Playa Del Rey CA), Integrating capacitively coupled transimpedance amplifier.
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