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A system and a method of testing a semiconductor die is provided. An embodiment comprises a plurality of metal tips that are connected to a redistribution layer that fans out the pitch from the tips to metal plugs located in the substrate. The metal tips could be formed using semiconductor processes

A system and a method of testing a semiconductor die is provided. An embodiment comprises a plurality of metal tips that are connected to a redistribution layer that fans out the pitch from the tips to metal plugs located in the substrate. The metal tips could be formed using semiconductor processes and either adding smaller layers of metal to larger layers of metal or else removing portions of one piece of metal to form the tips. The metal plugs are connected to a space transformation layer. The space transformation layer is electrically connected to a printed circuit board using, for example, a spring loaded connection such as a pogo pin. The space transformation layer is aligned onto the printed circuit board by a series of guidance mechanisms such as smooth fixtures, and the planarity of the tips is adjusted by adjusting a series of screws.

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What is claimed is: 1. A semiconductor device test structure, the test structure comprising: a substrate, the substrate having a first side and a second side, the first side and the second side being on opposing sides of the substrate; a plurality of metal plugs with a first pitch located within th

What is claimed is: 1. A semiconductor device test structure, the test structure comprising: a substrate, the substrate having a first side and a second side, the first side and the second side being on opposing sides of the substrate; a plurality of metal plugs with a first pitch located within the substrate, and extending through the substrate from the first side to the second side; first electrical connectors electrically connected to the plurality of metal plugs on the first side of the substrate; a first dielectric layer located over the substrate and the plurality of metal plugs on the second side of the substrate; a first metal layer located over the first dielectric layer, the first metal layer having a first plurality of separate sections, each of the first plurality of separate sections having a portion that extends through the first dielectric layer and being electrically connected to respective ones of the plurality of metal plugs, wherein the portion that extends through the first dielectric layer comprises a material that is solid at an operating temperature of the semiconductor device test structure; and a plurality of tips with a second pitch different from the first pitch located over respective ones of the first plurality of separate sections, the plurality of tips having an upper portion and a lower portion, the upper portion being smaller than the lower portion. 2. The semiconductor device test structure of claim 1, wherein the first pitch of the plurality of metal plugs is larger than the second pitch of the plurality of tips. 3. The semiconductor device test structure of claim 1, wherein the second pitch is less than about 50 μm. 4. The semiconductor device test structure of claim 1, wherein the plurality of tips comprises a nickel-cobalt alloy. 5. The semiconductor device test structure of claim 1, further comprising: a space transformation layer with a first set of contact pads on a first side of the space transformation layer, the first set of contact pads connected to the respective ones of the first electrical connectors, and a second set of contact pads located on an opposite side of the space transformation layer than the first set of contact pads, the second set of contact pads having a larger pitch than the first set of contact pads; and an underfill material formed between the substrate and the space transformation layer. 6. The semiconductor device test structure of claim 5, further comprising: a printed circuit board having a third set of contact pads; and compressible connectors between the third set of contact pads and the space transformation layer, the compressible connectors electrically connecting the third set of contact pads to respective ones of the second set of contact pads. 7. A semiconductor device test structure, the test structure comprising: a printed circuit board with a first set of contact pads; a space transformation layer over the printed circuit board, the space transformation layer comprising: a second set of contact pads on a first surface of the space transformation layer facing the printed circuit board; a third set of contact pads on a second surface of the space transformation layer opposite the printed circuit board, the third set of contact pads having a first pitch; and conductive lines electrically connecting the second set of contact pads and the third set of contact pads; a first plurality of connectors between the first set of contact pads and the second set of contact pads, the first plurality of connectors being arranged to have a second pitch that is larger than the first pitch; a substrate located over the space transformation layer; a plurality of metal plugs located within the substrate, and extending through the entire substrate; a second plurality of connectors electrically connected to the metal plugs on one side of the substrate, and also electrically connected to the third set of contact pads; a plurality of tips electrically connected to respective ones of the plurality of metal plugs and having a third pitch, the third pitch being smaller than the first pitch, the plurality of tips having an upper portion and a lower portion, the upper portion being smaller than the lower portion, the upper portion having a uniform width and extending away from the metal plugs at a right angle; and one or more metal layers located between the plurality of tips and the plurality of metal plugs, the one or more metal layers electrically connecting the plurality of tips to respective ones of the plurality of metal plugs. 8. The semiconductor device test structure of claim 7, further comprising a metal cap overlying each of the plurality of tips. 9. The semiconductor device test structure of claim 7, wherein the plurality of tips comprises a nickel-cobalt alloy. 10. The semiconductor device test structure of claim 7, wherein the first plurality of connectors comprise pogo pins. 11. The semiconductor device test structure of claim 7, further comprising: a bottom mounting fixture located on the printed circuit board; a top mounting fixture located over the bottom mounting fixture, the top mounting fixture having an extension that extends over at least a portion of the space transformation layer; and a plurality of screws connecting the top mounting fixture to the bottom mounting fixture. 12. The semiconductor device test structure of claim 7, further comprising a guidance mechanism arranged so as to ensure the proper alignment of the first plurality of electrical connections. 13. A semiconductor device test structure, the test structure comprising: a printed circuit board with a first plurality of contact pads; a space transformation layer over the circuit board, wherein the space transformation layer has a second plurality of contact pads on a first major surface of the space transformation layer facing the printed circuit board, and a third plurality of contact pads on a second major surface of the space transformation layer facing away from the printed circuit board, each contact pad of the third plurality of contact pads being electrically connected to one of the contact pads of the second plurality of contact pads, wherein the second plurality of contact pads has a first pitch and the third plurality of contact pads has a second pitch that is smaller than the first pitch; a first plurality of electrical connections connecting the first plurality of contact pads and the second plurality of contact pads; a substrate over the space transformation layer; a plurality of metal plugs extending through the substrate; a second plurality of electrical connections between respective ones of the plurality of metal plugs and the third plurality of contact pads; a first dielectric layer on an opposing side of the substrate from the second plurality of electrical connections; and a plurality of tips over the first dielectric layer and electrically connected to respective ones of the plurality of metal plugs through one or more metal layers, the plurality of tips having a third pitch that is smaller than the second pitch and having an upper portion that is smaller than a lower portion; wherein the one or more metal layers extend through the first dielectric layer with a uniform width. 14. The semiconductor device test structure of claim 13, further comprising a metal cap over each of the plurality of tips. 15. The semiconductor device test structure of claim 13, wherein the plurality of tips comprises a nickel-cobalt alloy. 16. The semiconductor device test structure of claim 13, wherein the first plurality of connectors comprises pogo pins. 17. The semiconductor device test structure of claim 13, wherein the third pitch is less than about 50 μm. 18. The semiconductor device test structure of claim 13, further comprising a plurality of screws extending through a top mounting fixture and to a bottom mounting fixture, the bottom mounting fixture being connected to the printed circuit board, and the top mounting fixture having a portion that extends over at least a portion of the space transformation layer. 19. The semiconductor device test structure of claim 13, wherein the one or more metal layers comprises three metal layers. 20. The semiconductor device test structure of claim 13, further comprising guides to position the space transformation layer relative to the printed circuit board, the guides further limiting movement of the space transformation layer relative to the printed circuit board to a direction substantially normal to a major surface of the printed circuit board.