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[미국특허] Method of fabricating module having stacked chip scale semiconductor packages 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/00
  • H01L-023/02
출원번호 UP-0125770 (2008-05-22)
등록번호 US-7645634 (2010-02-22)
발명자 / 주소
  • Karnezos, Marcos
출원인 / 주소
  • Stats Chippac Ltd.
인용정보 피인용 횟수 : 8  인용 특허 : 123

초록 ▼

Stacked CSP (chip scale package) modules include a molded first (“top”) chip scale package having a molding side and a substrate side, and a second (“bottom”) package affixed to the substrate side of the top chip scale package, the second package being electrically connec

대표청구항 ▼

What is claimed is: 1. A method for making a stacked package module, comprising providing a first chip scale package including at least one first package die affixed to and electrically interconnected with a die attach side of a first package substrate, the first CSP being molded and without solder

이 특허에 인용된 특허 (123) 인용/피인용 타임라인 분석

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  30. Chiang, Cheng-Lien, Method of forming a three-dimensional stacked semiconductor package device.
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  66. Tamaki Kazuo,JPX ; Saza Yasuyuki,JPX ; Dotta Yoshihisa,JPX, Semiconductor device using a chip scale package.
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  67. Mori Ryuichiro,JPX, Semiconductor module comprising semiconductor packages.
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  68. Karnezos,Marcos; Carson,Flynn, Semiconductor multi-package module having inverted bump chip carrier second package.
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  69. Karnezos,Marcos, Semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package.
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