초록 ▼

A light emitting display comprises: at least one first metal layer; a second metal layer crossing the first metal layer and having a first width; a light emitting device formed adjacent to a region where the first metal layer and the second metal layer cross each other; and a pixel circuit including

A light emitting display comprises: at least one first metal layer; a second metal layer crossing the first metal layer and having a first width; a light emitting device formed adjacent to a region where the first metal layer and the second metal layer cross each other; and a pixel circuit including at least one transistor which causes the light emitting device to emit light. The transistor comprises a semiconductor layer having a second width greater than the first width. With this configuration, in the light emitting display of the present invention, the semiconductor layer of the transistor is formed in a region where the source/drain metal layer and the gate metal layer cross each other, and has a width greater than that of the source/drain metal layer, so that the source/drain metal layer is disposed within the width of the semiconductor layer. Thus, a tip of the gate metal layer, formed in the grain and the pattern edge of the semiconductor layer, is not disposed within the region overlapping the source/drain metal layer so that generation of static electricity between the gate metal layer and the source/drain metal layer is prevented.

대표청구항 ▼

What is claimed is: 1. A light emitting display, comprising at least one first metal layer; a second metal layer crossing said at least one first metal layer and having a first width; a light emitting device formed adjacent to a region where said at least one first metal layer and the second metal

What is claimed is: 1. A light emitting display, comprising at least one first metal layer; a second metal layer crossing said at least one first metal layer and having a first width; a light emitting device formed adjacent to a region where said at least one first metal layer and the second metal layer cross each other; and a pixel circuit comprising at least one transistor for causing the light emitting device to emit light, and a driving transistor connected between a power line formed from said at least one first metal layer and the light emitting device, and including a gate terminal; wherein said at least one transistor comprises a semiconductor layer having a second width greater than the first width; and wherein the pixel circuit further comprises: a first capacitor having a first terminal connected to a first node, and having a second terminal connected to the gate terminal of the driving transistor; a first transistor controlled by a first scan signal applied to a first scan line formed from said at least one first metal layer, and connected between a data line formed from the second metal layer and the first node; a second transistor controlled by a second scan signal applied to a second scan line formed from said at least one first metal layer, and connected between the first node and the power line; a third transistor controlled by the second scan signal, and connected between the gate terminal of the driving transistor and a second node connected to an output terminal of the driving transistor; a fourth transistor controlled by the second scan signal, and connected between the second node and an anode electrode of the light emitting device; and a second capacitor connected between the first node and the power line. 2. The light emitting display according to claim 1, wherein said at least one first metal layer has a width which is uniform in a region which overlaps the semiconductor layer. 3. The light emitting display according to claim 1, wherein said at least one transistor further comprises: a first insulating layer formed on the semiconductor layer; a gate metal layer formed on the first insulating layer; a second insulating layer formed on the gate metal layer; and a source/drain metal layer formed on the second insulating layer. 4. The light emitting display according to claim 3, wherein the gate metal layer is included in said at least one first metal layer. 5. The light emitting display according to claim 3, wherein the source/drain metal layer is included in the second metal layer. 6. The light emitting display according to claim 1, wherein the third transistor and the fourth transistor differ from each other in arrangements of N and P type materials. 7. The light emitting display of claim 1, said at least one transistor comprising: a gate metal layer made from the same material as said at least one first metal layer, said gate metal layer having a width which is uniform in a region overlapping the semiconductor layer; and a source/drain metal layer made from the same material as said second metal layer. 8. The light emitting display of claim 1, said at least one transistor comprising: a first insulating layer formed to cover the semiconductor layer; a gate metal layer formed on the first insulating layer and made from the same material as said at least one first metal layer, said gate metal layer having a width which is uniform in a region overlapping the semiconductor layer; a second insulating layer formed to cover the gate metal layer; and a source/drain metal layer formed on said second insulating layer and made from the same material as said second metal layer. 9. The light emitting display of claim 1, said semiconductor layer being formed at said region where said at least one first metal layer and the second metal layer cross each other, and having a uniform width across said region where said at least one first metal layer and the second metal layer cross each other, a banding portion being formed outside of said region where said at least one first metal layer and the second metal layer cross each other. 10. The light emitting display of claim 1, said semiconductor layer being formed at the region where said at least one first metal layer and said second metal layer cross each other; said semiconductor layer having a line width, across the region where said at least one first metal layer and said second metal layer cross each other, which is greater than the first width of said second metal layer; and said at least one first metal layer having a uniform width across the region where said at least one first metal layer and said second metal layer cross each other, a banding portion being formed outside of said region where said at least one first metal layer and said second metal layer cross each other. 11. A light emitting display, comprising: at least one first metal layer; a second metal layer crossing said at least one first metal layer and having a first width; a light emitting device formed adjacent to a region where said at least one first metal layer and the second metal layer cross each other; a pixel circuit comprising at least one transistor for causing the light emitting device to emit light, wherein said at least one transistor comprises a semiconductor layer having a second width greater than the first width; and a driving transistor connected between the second metal layer and the light emitting device, said at least one transistor and said driving transistor each comprising: a gate metal layer made from the same material as said first metal layer; and a source/drain metal layer made from the same material as said second metal layer; said gate metal layer of said at least one transistor having a width which is uniform in a region overlapping the semiconductor layer; and wherein the pixel circuit further comprises: a first capacitor having a first terminal connected to a first node, and having a second terminal connected to the gate terminal of the driving transistor; a first transistor controlled by a first scan signal applied to a first scan line formed from said at least one first metal layer, and connected between a data line formed from the second metal layer and the first node; a second transistor controlled by a second scan signal applied to a second scan line formed from said at least one first metal layer, and connected between the first node and the power line; a third transistor controlled by the second scan signal, and connected between the gate terminal of the driving transistor and a second node connected to an output terminal of the driving transistor; a fourth transistor controlled by the second scan signal, and connected between the second node and an anode electrode of the light emitting device; and a second capacitor connected between the first node and the power line.