초록 ▼

An ambipolar transistor, including a p-type semiconductor region and an n-type semiconductor region near the p-type semiconductor region. Also a first terminal and second terminal contact both the p-type semiconductor region and the n-type semiconductor region. Furthermore, the p-type semiconductor

An ambipolar transistor, including a p-type semiconductor region and an n-type semiconductor region near the p-type semiconductor region. Also a first terminal and second terminal contact both the p-type semiconductor region and the n-type semiconductor region. Furthermore, the p-type semiconductor region and the n-type semiconductor region substantially do not overlap each other. A method of manufacturing an ambipolar transistor is also disclosed, including forming a p-type semiconductor region, forming an n-type semiconductor region near the p-type semiconductor region, forming a first terminal contacting both the p-type semiconductor region and n-type semiconductor region, forming a second terminal contacting both the p-type semiconductor region and n-type semiconductor region; and wherein the p-type semiconductor region and the n-type semiconductor region substantially do not overlap, and have substantially no interfacial area.

대표청구항 ▼

What is claimed is: 1. An ambipolar transistor, comprising: a p-type semiconductor region comprising a first semiconductor material; an n-type semiconductor region comprising a second semiconductor material that is different from the first semiconductor material; a first terminal contacting both th

What is claimed is: 1. An ambipolar transistor, comprising: a p-type semiconductor region comprising a first semiconductor material; an n-type semiconductor region comprising a second semiconductor material that is different from the first semiconductor material; a first terminal contacting both the p-type semiconductor region and the n-type semiconductor region; and a second terminal contacting both the p-type semiconductor region and the n-type semiconductor region, wherein the p-type semiconductor region and the n-type semiconductor region substantially do not overlap. 2. The ambipolar transistor of claim 1, wherein the ratio of the channel width of the p-type region to the channel width of the n-type region is from about 9:1 to about 1:9 so that the p-type semiconductor region and the n-type semiconductor region have a balanced current. 3. The ambipolar transistor of claim 1, wherein the ratio of the channel width of the p-type region to the channel width of n-type region is from about 7:3 to about 3:7 so that the p-type semiconductor region and the n-type semiconductor region have a balanced current. 4. The ambipolar transistor of claim 1, wherein the p-type semiconductor region and the n-type semiconductor region have substantially no interfacial area. 5. The ambipolar transistor of claim 1, wherein the overlap area between the p-type semiconductor region and the n-type semiconductor region is less than 50% of the total area of the p-type semiconductor region and the n-type semiconductor region. 6. The ambipolar transistor of claim 1, wherein the overlap area between the p-type semiconductor region and the n-type semiconductor region is less than 5% of the total area of the p-type semiconductor region and the n-type semiconductor region. 7. The ambipolar transistor of claim 1, wherein the p-type semiconductor region and the n-type semiconductor region are laterally arranged. 8. A method of manufacturing an ambipolar transistor, comprising: forming a p-type semiconductor region comprising a first semiconductor material; forming an n-type semiconductor region near the p-type semiconductor region and comprising a second semiconductor material different from the first semiconductor material; forming a first terminal; and forming a second terminal wherein both the first terminal and the second terminal contact both the p-type semiconductor region and the n-type semiconductor region, and wherein the p-type semiconductor region and the n-type semiconductor region substantially do not overlap. 9. The method of claim 8, wherein the p-type semiconductor region is formed by inkjet printing a p-type semiconductor composition. 10. The method of claim 8, wherein both the p-type semiconductor region and the n-type semiconductor region are formed by inkjet printing. 11. The method of claim 8, wherein the overlap area between the p-type semiconductor region and the n-type semiconductor region is less than 20% of the total area of the p-type semiconductor region and the n-type semiconductor region. 12. The method of claim 8, further comprising modifying the gate dielectric layer with poly-methyl silsequinoxane. 13. The method of claim 12, further comprising forming a precursor layer on the modified gate dielectric layer. 14. The method of claim 13, wherein the p-type semiconductor region comprises a polythiophene semiconductor. 15. The method of claim 13, wherein the forming the n-type semiconductor region further includes: heating a precursor layer at about 180° Celsius for about 30 minutes; cooling the precursor layer to room temperature; and re-heating the precursor layer at about 400° Celsius for about 30 minutes to form the n-type semiconductor region. 16. The method of claim 8, wherein the p-type semiconductor region and the n-type semiconductor region have substantially no interfacial area. 17. The method of claim 8, further comprising: laterally arranging the p-type semiconductor region and the n-type semiconductor region with respect to each other. 18. A system for manufacturing a circuit with a plurality of ambipolar transistors, the system comprising: means for forming a p-type semiconductor region comprising a first semiconductor material; means for forming an n-type semiconductor region near the p-type semiconductor region and comprising a second semiconductor material that is different from the first semiconductor material; means for forming a first terminal contacting both the p-type semiconductor region and the n-type semiconductor region; and means for forming a second terminal contacting both the p-type semiconductor region and the n-type semiconductor region, wherein the p-type semiconductor region and the n-type semiconductor region have substantially no overlap. 19. The system of claim 18, wherein both the p-type semiconductor and the n-type semiconductor are solution processable semiconductors, the p-type semiconductor being an organic semiconductor, and the n-type semiconductor being an inorganic semiconductor. 20. The system of claim 18, wherein the p-type semiconductor is a polythiophene and the n-type semiconductor is a metal oxide. 21. The system of claim 18, wherein the p-type semiconductor region and the n-type semiconductor region are laterally arranged.