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Quad Flat No-Lead (QFN) packages are provided. An embodiment of a QFN package includes a semiconductor chip including an active surface and an inactive surface, a plurality of leads, a plurality of wire bonds configured to couple the plurality of leads to the semiconductor chip, and a mold material

Quad Flat No-Lead (QFN) packages are provided. An embodiment of a QFN package includes a semiconductor chip including an active surface and an inactive surface, a plurality of leads, a plurality of wire bonds configured to couple the plurality of leads to the semiconductor chip, and a mold material including a mounting side and having a perimeter. The active surface is oriented toward the mounting side, the plurality of wire bonds are disposed between the active surface and the mounting side within the mold material, and the plurality of leads are exposed on the mounting side and are at least partially encapsulated within the perimeter of the mold material.

대표청구항 ▼

We claim: 1. A Quad Flat No-Lead (QFN) package, the QFN package comprising: a semiconductor chip including an active surface and an inactive surface; a plurality of leads, wherein peripheral portions of the active surface are disposed on the plurality of leads; a plurality of wire bonds configured

We claim: 1. A Quad Flat No-Lead (QFN) package, the QFN package comprising: a semiconductor chip including an active surface and an inactive surface; a plurality of leads, wherein peripheral portions of the active surface are disposed on the plurality of leads; a plurality of wire bonds configured to couple the plurality of leads to the semiconductor chip; and a mold material including a mounting side and having a perimeter, wherein the active surface is oriented toward the mounting side, the plurality of wire bonds are disposed between the active surface and the mounting side within the mold material, and the plurality of leads are exposed on the mounting side and are at least partially encapsulated within the mold material. 2. The QFN package of claim 1, wherein the plurality of leads each include a height in a range of about 0.15 mm to about 0.4 mm. 3. A quad Flat No-Lead (QFN) package, the QFN package comprising: a semiconductor chip including an active surface and an inactive surface; a plurality of leads; a plurality of wire bonds configured to couple the plurality of leads to the semiconductor chip; and a mold material including a mounting side and having a perimeter, wherein the active surface is oriented toward the mounting side, the plurality of wire bonds are disposed between the active surface and the mounting side within the mold material, and the plurality of leads are exposed on the mounting side and are at least partially encapsulated within the mold material, wherein the plurality of leads comprises at least one mold lock coupling each of the plurality of leads to the mold material. 4. The QFN package of claim 1, wherein each of the plurality of leads has a jogged-shape. 5. The QFN package of claim 4, wherein the jogged shape has a two-tiered surface oriented toward the mounting side, and wherein at least one wire bond is coupled to the active side and the two-tiered surface. 6. The QFN package of claim 5, further comprising a top side located substantially opposite the mounting side and a plurality of lateral sides, wherein: a first center of the semiconductor chip is oriented substantially in a second center of the QFN package, and the second center is located at a center of the mounting side, the top side, and the plurality of sides. 7. The QFN package of claim 5, wherein a width of the mounting side is not greater than about 2.5 mm. 8. The QFN package of claim 7, wherein a height of the QFN package is not greater than about 1 mm. 9. The QFN package of claim 5, wherein a ratio of a width of the QFN package to a width of the semiconductor chip is not greater than 1.2. 10. A Quad Flat No-Lead (QFN) package comprising: a mold material including a mounting side; a first semiconductor chip including a first active surface and a first inactive surface, wherein the first active surface is oriented toward the mounting side; a second semiconductor chip including a second active surface and a second inactive surface; a first plurality of leads oriented on the mounting side, wherein peripheral portions of the first active surface are disposed on the first plurality of leads; and a first plurality of wire bonds coupling the first plurality of leads to the first semiconductor chip, wherein the first plurality of wire bonds are disposed between the first active surface and the mounting side. 11. A quad Flat No-Lead (QFN) package comprising: a mold material including a mounting side; a first semiconductor chip including a first active surface and a first inactive surface, wherein the first active surface is oriented toward the mounting side; a second semiconductor chip including a second active surface and a second inactive surface; a first plurality of leads oriented on the mounting side; a first plurality of wire bonds coupling the first plurality of leads to the first semiconductor chip, wherein the first plurality of wire bonds are disposed between the first active surface and the mounting side; a second plurality of leads oriented on the mounting side; and a second plurality of wire bonds coupling the second plurality of leads to the second semiconductor chip, wherein the second plurality of wire bonds are disposed between the second active surface and the mounting side. 12. The QFN package of claim 11, further comprising: a first wire bond coupling a first lead to the first active side, wherein the first wire bond is disposed between the first active surface and the mounting side. 13. The QFN package of claim 12, further comprising: a second wire bond coupling the first lead to the second active side, wherein the second wire bond is disposed between the second active surface and the mounting side. 14. The QFN package of claim 11, wherein the first plurality of leads and second plurality of leads each comprise at least one mold lock coupling each of the first plurality of leads and the second plurality of leads to the mold material. 15. The QFN package of claim 11, wherein each of the first plurality of leads and the second plurality of leads comprise a jogged-shape to couple each of the first plurality of leads and the second plurality of leads to the mold material. 16. The QFN package of claim 10, wherein the first plurality of leads each include a height in a range of about 0.15 mm to about 0.4 mm. 17. A Quad Flat No-Lead (QFN) package, the QFN package comprising: a semiconductor chip including an active surface and an inactive surface; a mold material including a mounting side, a top side, and a perimeter, wherein the active surface is oriented toward the mounting side; a plurality of leads arranged around a perimeter of the QFN package, wherein the active surface is disposed on the plurality of leads, and the plurality of leads are exposed on the mounting side and are at least partially encapsulated within the mold material; and a plurality of wire bonds configured to couple the plurality of leads to the semiconductor chip, wherein the plurality of wire bonds are disposed between the active surface and the mounting side within the mold material. 18. The QFN package of claim 17, further comprising: an adhesive material disposed between the active side and the leads. 19. The QFN package of claim 17, wherein the plurality of leads are included entirely within the perimeter of the mold material. 20. The QFN package of claim 17, wherein the active side is higher than the plurality of leads in that the active side is closer to the top side of the mold material than the plurality of leads.