이 특허에 인용된 특허 (206) 인용/피인용 타임라인 분석

1. Nguyen, Luu; Murray, Cade; Deane, Peter; Tsay, Chen-Hui, Arrayable, scaleable, and stackable molded package configuration.

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2. Makoto Terui JP, BGA package and method for fabricating the same.

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3. Fee, Setho Sing; Chye, Lim Thiam; Heppler, Steven W.; Yin, Leng Nam; Tan, Keith; Guay, Patrick; Tian, Edmund Lua Koon; Eng, Yap Kah; Seng, Eric Tan Swee, Ball grid array interposer, packages and methods.

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4. Kaul Sunil (Fremont CA) Laird Douglas A. (Los Gatos CA), Ball grid array packages for high speed applications.

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5. Kinsman,Larry D., Bumped die and wire bonded board-on-chip package.

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6. Koopmans, Michel, Bumping technology in stacked die configurations.

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7. Culnane Thomas Moran ; Gaynes Michael Anthony ; Seto Ping Kwong ; Shaukatullah Hussain, Chip carrier modules with heat sinks attached by flexible-epoxy.

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8. Akram, Salman, Chip package with grease heat sink.

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9. Shyue Fong Quek MY; Ying Keung Leung SG; Sang Yee Loong SG; Ting Cheong Ang SG, Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection.

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10. Ference Thomas George ; Howell Wayne John ; Sprogis Edmund Juris, Chip-on-chip interconnections of varied characteristics.

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11. Chen, Yu; Gerber, Joel A.; Schreiber, Brian E.; Smith, Joshua W., Circuit elements using z-axis interconnect.

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12. Bozso Ferenc Miklos ; Emma Philip George, Clock skew minimization system and method for integrated circuits.

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13. Tago,Masamoto, Compact semiconductor device capable of mounting a plurality of semiconductor chips with high density and method of manufacturing the same.

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14. Heim Craig G. ; Hooker Wade Leslie ; Trivedi Ajit Kumar, Cooling structure for electronic components.

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15. Wu, Chi-Chuan; Huang, Chien-Ping, Crack-preventive semiconductor package.

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16. Barrow Michael, Custom corner attach heat sink design for a plastic ball grid array integrated circuit package.

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17. Appelt, Bernd Karl; Johansson, Gary Alan; Papathomas, Konstantinos I., Die attachment with reduced adhesive bleed-out.

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18. Doan,Trung T., Die-wafer package and method of fabricating same.

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19. Choi, Ill Heung, Duel die package.

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20. Gebauer, Uta; Hedler, Harry; H?gerl, J?rgen; Strutz, Volker, Electronic component with a semiconductor chip and method for producing the electronic component.

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21. Combs, Edward G.; Sheppard, Robert P.; Pun, Tai Wai; Ng, Hau Wan; Fan, Chun Ho; McLellen, Neil Robert, Enhanced thermal dissipation integrated circuit package.

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22. McGhee, Andrew; Keeble, Daniel John; Pozzi, Fabio; Lemoff, Brian, Environmental protection for an optical assembly and method therefor.

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23. Webster, Steven; Arellano, Tony; Hollaway, Roy Dale, Fabrication method for integrally connected image sensor packages having a window support in contact with the window and active area.

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24. Moden Walter L., Flip chip adaptor package for bare die.

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25. Moden, Walter L., Flip chip adaptor package for bare die.

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26. Moden, Walter L., Flip chip adaptor package for bare die.

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27. Kinsman, Larry D., Flip-chip image sensor packages.

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28. Beroz,Masud; Warner,Michael; Smith,Lee; Urbish,Glenn; Kang,Teck Gyu; Park,Jae M.; Kubota,Yoichi, High frequency chip packages with connecting elements.

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29. Song, Young-Jae; Kwon, Young-Shin; Youm, Kun-Dae; Kim, Young-Soo, Higher-density memory card.

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30. Bertin Claude Louis ; Ference Thomas George ; Howell Wayne John ; Sprogis Edmund Juris, Highly integrated chip-on-chip packaging.

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31. Bertin Claude Louis ; Ference Thomas George ; Howell Wayne John ; Sprogis Edmund Juris, Highly integrated chip-on-chip packaging.

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32. Beyne, Eric; Lerner, Steve, Image sensor ball grid array package and the fabrication thereof.

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33. Webster, Steven, Image sensor package.

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34. Chiu,Anthony M.; Siegel,Harry Michael, Integrated circuit package with exposed die surfaces and auxiliary attachment.

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35. Michael G. Kelly ; James-Yu Chang ; Gary Dean Sasser ; Andrew Arthur Hunter GB; Cheng-Cheng Chang, Integrated circuit packaging for optical sensor devices.

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36. Akram, Salman; Wood, Alan G.; Farnworth, Warren M., Interposer and methods for fabricating same.

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37. Hembree David R., Interposer for semiconductor components having contact balls.

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38. Hisashi Takeda JP, Interposer for separating stacked semiconductor chips mounted on a multi-layer printed circuit board.

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39. Davis Nancy L. (Boise ID), Lead frame for semiconductor devices having improved adhesive bond line control.

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40. Matsuzawa, Hideki; Hayashi, Shintaro, Leadframe and method of manufacturing a semiconductor device using the same.

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41. Minamio, Masanori; Adachi, Osamu, Leadframe for a semiconductor device having leads with land electrodes.

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42. Chien-Ping Huang TW, Leadless image sensor package structure and method for making the same.

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43. Maeda, Takehiko; Tsukano, Jun, Light thin stacked package semiconductor device and process for fabrication thereof.

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44. Yasumoto Masami (Tottori-ken JPX) Motoike Tatsuya (Tottori JPX), Linear light source.

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45. Rong-Fong Huang ; Chia-Yu Fu, Low profile interconnect structure.

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46. Melton Cynthia M. (Bolingbrook IL) Cholewczynski Kenneth (Streamwood IL) Moore Kevin D. (Schaumburg IL) Raleigh Carl (Cary IL), Low temperature method for forming solder bump interconnections to a plated circuit trace.

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47. Anthony J. LoBianco ; Frank J. Juskey ; Stephen G. Shermer ; Vincent DiCaprio ; Thomas P. Glenn, Making semiconductor packages with stacked dies and reinforced wire bonds.

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48. Lee Shaw Wei (San Jose CA), Maximized substrate design for grid array based assemblies.

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49. Nguyen Luu ; Prabhu Ashok ; Kelkar Nikhil ; Takiar Hem P., Method and apparatus for forming a plastic chip on chip package module.

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50. Ong, Ee Chang, Method and apparatus for reducing IC die mass and thickness while improving strength characteristics.

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51. Fukasawa, Norio; Kawahara, Toshimi; Morioka, Muneharu; Osawa, Mitsunada; Shinma, Yasuhiro; Matsuki, Hirohisa; Onodera, Masanori; Kasai, Junichi; Maruyama, Shigeyuki; Sakuma, Masao; Suzuki, Yoshimi; T, Method and mold for manufacturing semiconductor device, semiconductor device and method for mounting the device.

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52. Akram,Salman; Wood,Alan G.; Farnworth,Warren M., Method for fabricating an interposer.

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53. Sakuyama, Seiki; Yamagishi, Yasuo; Mizukoshi, Masataka, Method for forming bumps, semiconductor device, and solder paste.

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54. Melton Cynthia (Bolingbrook IL) Raleigh Carl (Cary IL) Cholewczynski Kenneth (Streamwood IL) Moore Kevin (Schaumburg IL), Method for forming solder bump interconnections to a solder-plated circuit trace.

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55. Riding Alan J. ; Jones H. Wayne ; Pennisi Leonard, Method for producing thin dice from fragile materials.

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56. Akram Salman ; Brooks Jerry M., Method of constructing stacked packages.

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57. Huang Chien Ping,TWX ; Huang Yang Chun,TWX ; Yu Kevin,TWX ; Chen Sheng-Fang,TWX, Method of encapsulating a chip.

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58. Huang Chien Ping,TWX, Method of fabricating an integrated circuit package having a core-hollowed encapsulation body.

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59. Koopmans, Michel, Method of fabricating stacked die configurations utilizing redistribution bond pads.

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60. Ball Michael B., Method of fabrication of stacked semiconductor devices.

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61. Caletka, David V.; Johnson, Eric A., Method of forming BGA interconnections having mixed solder profiles.

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62. Chiang, Cheng-Lien, Method of forming a three-dimensional stacked semiconductor package device.

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63. Thomas P. Glenn, Method of making a plastic package for an optical integrated circuit device.

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64. Glenn, Thomas P.; Smith, Lee J.; Zoba, David A.; Ramakrishna, Kambhampati; DiCaprio, Vincent, Method of making a semiconductor package including stacked semiconductor dies.

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65. Glenn Thomas P., Method of making an integrated circuit package employing a transparent encapsulant.

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66. Chun Hung Lin TW, Method of making semiconductor packages at wafer level.

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67. Vincent Lin TW; Chi Ming Chang TW, Method of making substrate for use in forming image sensor package.

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68. Chun-Chi Lee TW, Method of making wafer level chip scale package.

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69. Tomihara, Seiichi, Method of manufacturing a semiconductor device having flexible wiring substrate.

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70. Chien Ping Huang TW, Method of manufacturing an image-sensor integrated circuit package without resin flash on lead frame and with increased wire bondability.

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71. Hashimoto Nobuaki,JPX, Method of mounting a sealed assembly on a mounting substrate and optical transducer.

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72. Mong, Weng Khoon; Cheong, Yew Wee; Gan, Eng Chiang; Loke, Mun Leong, Method of thinning a wafer utilizing a laminated reinforcing layer over the device side.

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73. Kakimoto Noriko,JPX ; Suematsu Eiji,JPX, Millimeter wave semiconductor device.

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74. Pu, Han-Ping; Huang, Chih-Ming; Huang, Chien-Ping, Module device of stacked semiconductor packages and method for fabricating the same.

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75. Glenn Thomas P. ; Webster Steven, Molded window array for image sensor packages.

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76. Michael B. Ball, Multi-chip device utilizing a flip chip and wire bond assembly.

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77. Ming-Hsun Lee TW; Chin-Te Chen TW, Multi-chip module.

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78. Kang,In Ku; Choi,Hee Kook; An,Sang Ho; Lee,Sang Yeop, Multi-chip module having bonding wires and method of fabricating the same.

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79. Vaiyapuri Venkateshwaran,SGX ; Yang Jicheng,SGX, Multi-chip module with stacked dice.

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80. Kim Jae Myun,KRX, Multi-chip package.

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81. Liu,Cheng Cheng, Multi-chip package combining wire-bonding and flip-chip configuration.

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82. Ball Michael B., Multi-chip stacked devices.

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83. Londa Joseph Michael, Multi-electronic device package.

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84. Londa Joseph Michael, Multi-electronic device package.

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85. Londa Joseph Michael, Multi-electronic device package comprising at least two substrates and at least four layers of electrically conductive.

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86. Kao-Yu Hsu TW; Su Tao TW, Multichip module.

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87. Fogal Rich (Boise ID) Ball Michael B. (Boise ID), Multichip module having a stacked chip arrangement.

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88. Lin Chun Hung,TWX, Multichip module having stacked chip arrangement.

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89. Miremadi Jian ; Schuyler Marc P., Multiple chip assembly.

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90. Michii, Kazunari; Akiyama, Tatsuhiko, Multiple chip package semiconductor device.

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91. Bayan, Jaime; Spalding, Peter Howard, Multiple row fine pitch leadless leadframe package with use of half-etch process.

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92. Lo, Randy H. Y.; Huang, Chien-Ping; Wu, Chi-Chuan, Multiple stacked-chip packaging structure.

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93. Jeansonne Jeff K., Opposed ball grid array mounting.

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94. Tao, Su; Yee, Kuo Chung; Kao, Jen Chieh; Chen, Chih Lung; Liau, Hsing Jung, Optical integrated circuit element package and process for making the same.

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95. Bauer Fred T. ; Stam Joseph Scott, Optical sensor package and method of making same.

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96. Rissing, Lutz; Obermayer, Florian; Schroll, Florian, Optoelectronic component using two encapsulating materials and the method of making the same.

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97. Shim, Il Kwon; Chow, Seng Guan; Balanon, Gerry, PBGA substrate for anchoring heat sink.

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98. Junichi Asada JP, Package having very thin semiconductor chip, multichip module assembled by the package, and method for manufacturing the same.

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99. Chen, Jian-Cheng; Hsiao, Wei-Min, Package of a chip with beveled edges.

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100. Chye, Lim Thiam; Fee, Setho Sing; Seng, Eric Tan Swee, Packaged microelectronic component assemblies.

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101. Gleim Robert D. (Newtown PA) de Grandpre Mark P. (Ambler PA), Positive photoresists containing preformed polyglutarimide polymer.

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102. Liou Shiann-Ming (Campbell CA), Process of forming conductive bumps on the electrodes of semiconductor chips using lapping and the bumps thereby created.

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103. Hsu, Chi-Hsing, Quad flat no-lead chip carrier.

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104. Uchida, Yasufumi; Saeki, Yoshihiro, Rearrangement sheet, semiconductor device and method of manufacturing thereof.

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105. Belgacem Haba ; Donald V. Perino ; Sayeh Khalili, Redistributed bond pads in stacked integrated circuit die package.

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106. Ichinose, Michihiko; Takizawa, Tomoko; Honda, Hirokazu; Kata, Keiichirou, Resin-encapsulated semiconductor device.

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107. Kondo, Takashi; Bando, Koji; Shibata, Jun; Narutaki, Kazuko, Resin-sealed chip stack type semiconductor device.

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108. Brooks, Jerry M., Semiconductor assembly without adhesive fillets.

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109. Brooks, Jerry M., Semiconductor assembly without adhesive fillets.

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110. Higashiguchi Masahiro,JPX, Semiconductor chip mounting board and a semiconductor device using same board.

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111. Swnson,Leland; Howard,Gregory Eric, Semiconductor circuit with multiple contact sizes.

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112. Klein,Dean A.; Wood,Alan G.; Doan,Trung Tri, Semiconductor component having multiple stacked dice.

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113. Hideki Ishii JP; Kazunari Michii JP; Jun Shibata JP; Moriyoshi Nakashima JP, Semiconductor device.

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114. Hirose, Masahiro, Semiconductor device.

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115. Ichikawa, Sunji, Semiconductor device.

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116. Ozawa Kaname,JPX ; Okuda Hayato,JPX ; Hiraoka Tetsuya,JPX ; Sato Mitsutaka,JPX ; Akashi Yuji,JPX ; Okada Akira,JPX ; Harayama Masahiko,JPX, Semiconductor device.

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117. Tadashi Komiyama JP, Semiconductor device.

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118. Terui, Makoto, Semiconductor device.

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119. Sakai Kunito (Hyogo JPX) Matsuda Sadamu (Hyogo JPX) Takahama Takashi (Hyogo JPX), Semiconductor device and manufacturing method therefor.

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120. Kurita, Yoichiro; Shironouchi, Toshiaki; Tetsuka, Takashi, Semiconductor device and method for manufacturing the same.

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121. Ohuchi Shinji,JPX ; Yamada Shigeru,JPX ; Shiraishi Yasushi,JPX, Semiconductor device and method for manufacturing the same.

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122. Takahashi Takuya,JPX ; Katsumata Akio,JPX, Semiconductor device and method for manufacturing the same.

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123. Nakayama, Hirohisa; Taniguchi, Jun; Abe, Takashi; Nakayama, Toshinori, Semiconductor device and method of fabricating the same, circuit board, and electronic equipment.

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124. Emoto, Yoshiaki, Semiconductor device and method of making the same, circuit board and electronic equipment.

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125. Ito, Fujio; Suzuki, Hiromicti, Semiconductor device and method of manufacturing the same.

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126. Kawakita Tetsuo,JPX ; Matsumura Kazuhiko,JPX ; Yamane Ichiro,JPX, Semiconductor device and method of manufacturing the same.

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127. Ichinose, Michihiko, Semiconductor device and packaging method thereof.

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128. Sahara Kunizo (Tokyo JPX) Otsuka Kanji (Higashiyamato JPX) Ishida Hisashi (Higashiyamato JPX), Semiconductor device and process for producing the same.

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129. Jiang, Tongbi; Fee, Setho Sing; Yean, Tay Wuu; Chye, Lim Thiam, Semiconductor device assemblies and packages including multiple semiconductor devices and methods.

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130. Higashiguchi Yutaka,JPX ; Kumai Toshio,JPX ; Teshima Yasuhiro,JPX ; Niishiro Mamoru,JPX ; Kobayashi Yasushi,JPX ; Sekiya Yukio,JPX ; Igarashi Shuzo,JPX ; Ichihara Yasuhiro,JPX, Semiconductor device having a bump which is inspected from outside and a circuit board used with such a semiconductor de.

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131. Yamawaki Masao (Itami JPX) Kondo Takashi (Itami JPX), Semiconductor device having a light transparent window and a method of producing same.

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132. Fumihiko Taniguchi JP; Akira Takashima JP, Semiconductor device having an interconnecting post formed on an interposer within a sealing resin.

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133. Brooks J. Mike ; Wood Alan G. ; Duesman Kevin G., Semiconductor device having ball-bonded pads.

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134. Kawakita Tetsuo,JPX ; Matsumura Kazuhiko,JPX ; Yamane Ichiro,JPX, Semiconductor device having improved test electrodes.

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135. Uchida, Yasufumi, Semiconductor device having multi-chip package.

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136. Yamada Yutaka,JPX ; Muramoto Takanori,JPX, Semiconductor device manufacturing method for grinding and dicing a wafer from a back side of the wafer.

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137. Tsukahara,Norihito; Akiguchi,Takashi; Miyakawa,Hidenori, Semiconductor device package manufacturing method and semiconductor device package manufactured by the method.

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138. Tamaki Kazuo,JPX ; Saza Yasuyuki,JPX ; Dotta Yoshihisa,JPX, Semiconductor device using a chip scale package.

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139. Mori Ryuichiro,JPX, Semiconductor module comprising semiconductor packages.

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140. Karnezos,Marcos; Carson,Flynn, Semiconductor multi-package module having inverted bump chip carrier second package.

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141. Karnezos,Marcos, Semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package.

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142. Karnezos,Marcos, Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package.

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143. Karnezos, Marcos, Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package.

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144. Karnezos,Marcos, Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package.

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145. Karnezos,Marcos, Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package.

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146. Karnezos,Marcos, Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages.

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147. Karnezos,Marcos, Semiconductor multi-package module having wire bond interconnect between stacked packages.

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148. Karnezos, Marcos, Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield.

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149. Karnezos, Marcos, Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages.

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150. Karnezos,Marcos, Semiconductor multipackage module including processor and memory package assemblies.

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151. Liao, Chih-Chin; Pu, Han-PIng; Huang, Chien-Ping, Semiconductor package.

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152. Park, Kye Chan, Semiconductor package and fabrication method of the same.

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153. JiYoung Chung KR, Semiconductor package and method for fabricating the same.

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154. Chien-Ping Huang TW, Semiconductor package configuration based on lead frame having recessed and shouldered portions for flash prevention.

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155. Tzu Chung-Hsing,TWX, Semiconductor package having multi-dies.

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156. Heo, Young Wook, Semiconductor package having stacked semiconductor chips and method of making the same.

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157. Huang, Chien-Ping, Semiconductor package with flash-proof device.

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158. Akram, Salman; Brooks, Jerry M., Semiconductor package with stacked substrates and multiple semiconductor dice.

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159. Karnezos,Marcos, Semiconductor stacked multi-package module having inverted second package.

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160. Karnezos, Marcos, Semiconductor stacked multi-package module having inverted second package and electrically shielded first package.

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161. Lin Paul T. (Austin TX), Shielded liquid encapsulated semiconductor device and method for making the same.

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162. Takahashi Nobuaki,JPX ; Kyougoku Yoshitaka,JPX ; Hashimoto Katsumasa,JPX ; Miyazaki Shinichi,JPX, Shock resistant semiconductor device and method for producing same.

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163. De Givry Jacques (Les Loges En Josas FRX), Solid state memory modules and memory devices including such modules.

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164. Yang,Chaur Chin; Wang,Hsueh Te, Stack type flip-chip package.

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165. Warren M. Farnworth ; Alan G. Wood ; Mike Brooks, Stackable semiconductor package having conductive layer and insulating layers and method of fabrication.

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166. Kim,Jung Jin, Stacked BGA packages.

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167. Tao Su,TWX ; Lo Kuang-Lin,TWX ; Chou Kuang-Chun,TWX ; Chen Shih-Chih,TWX, Stacked chip assembly utilizing a lead frame.

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168. McMahon, John F., Stacked chip packaging.

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169. Akram Salman, Stacked leads-over chip multi-chip module.

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170. Mess, Leonard E.; Brooks, Jerry M.; Corisis, David J., Stacked mass storage flash memory package.

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171. Corisis, David J., Stacked microelectronic dies and methods for stacking microelectronic dies.

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172. Degani, Yinon; Dudderar, Thomas Dixon; Sun, Liguo; Zhao, Meng, Stacked module package.

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173. Takiar Hem P. (Fremont CA) Lin Peng-Cheng (Cupertino CA), Stacked multi-chip modules and method of manufacturing.

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174. Fujitani,Hisaki; Itou,Fumito; Akahoshi,Toshitaka; Fukuda,Toshiyuki, Stacked semiconductor device.

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175. Kikuma, Katsuhito; Ikeda, Mitsutaka; Tsukidate, Yoshihiro; Akashi, Yuji; Ozawa, Kaname; Takashima, Akira; Nishimura, Takao, Stacked semiconductor device and method of producing the same.

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176. Kikuma, Katsuhito; Ikeda, Mitsutaka; Tsukidate, Yoshihiro; Akashi, Yuji; Ozawa, Kaname; Takashima, Akira; Uno, Tadashi; Nishimura, Takao; Ando, Fumihiko; Onodera, Hiroshi; Okuda, Hayato, Stacked semiconductor device and method of producing the same.

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177. St. Amand, Roger D.; Perelman, Vladimir, Stacked semiconductor die assembly having at least one support.

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178. Baek, Joong-hyun; Lee, Jin-yang; Im, Yun-hyeok; Lee, Tae-koo, Stacked semiconductor module and method of manufacturing the same.

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179. Pedron, Jr., Serafin P., Stacked semiconductor package and method of manufacturing the same.

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180. Shim, Il Kwon; Ramakrishna, Kambhampati; Chow, Seng Guan; Han, Byung Joon, Stacked semiconductor packages and method for the fabrication thereof.

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181. Jichen Wu TW; Meng Ru Tsai TW; Nai Hua Yeh TW; Chen Pin Peng TW, Stacked structure of semiconductor means and method for manufacturing the same.

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182. St. Amand,Roger D.; Kim,InTae; Perelman,Vladimir, Stacked-die extension support structure and method thereof.

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