IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
|
| 국제특허분류(IPC7판) |
|
| 출원번호 |
UP-0606621
(2006-11-30)
|
| 등록번호 |
US-7655909
(2010-03-31)
|
|
발명자
/ 주소 |
- Schimert, Thomas R.
- Syllaios, Athanasios J.
- McCardel, William L.
- Gooch, Roland W.
|
| 출원인 / 주소 |
- L-3 Communications Corporation
|
| 대리인 / 주소 |
O'Keefe, Egan, Peterman & Enders LLP
|
| 인용정보 |
피인용 횟수 :
8 인용 특허 :
91 |
초록
Infrared detector elements and methods for forming infrared detector elements in which the top metal layer of CMOS circuitry of the detector element is employed as a lead metal reflector for the infrared detector.
대표청구항
▼
What is claimed is: 1. An infrared detector element, comprising: a microbolometer infrared radiation detector structure, said microbolometer infrared detector structure comprising a lead metal reflector; wherein said lead metal reflector comprises an at least partially exposed planar top metal laye
What is claimed is: 1. An infrared detector element, comprising: a microbolometer infrared radiation detector structure, said microbolometer infrared detector structure comprising a lead metal reflector; wherein said lead metal reflector comprises an at least partially exposed planar top metal layer of read out integrated circuitry (ROIC) that is configured as said lead metal reflector for said microbolometer infrared detector structure. 2. The infrared detector element of claim 1, further comprising at least one input pad for said ROIC, said input pad comprising a portion of said at least partially exposed top metal layer of said ROIC. 3. The infrared detector element of claim 1, wherein said microbolometer infrared radiation detector structure comprises a diffractive resonant cavity (DRC) microbolometer structure. 4. The infrared detector element of claim 1, wherein said ROIC comprises CMOS circuitry; and wherein an at least partially exposed planar top metal layer of said CMOS circuitry is configured as said lead metal reflector for said microbolometer structure. 5. The infrared detector element of claim 1, wherein said ROIC is disposed on a first side of a substrate; wherein said microbolometer infrared radiation detector structure is disposed on said first side of said substrate; and wherein said ROIC further comprises: at least one additional planar metal layer disposed between said at least partially exposed planar top metal layer and said substrate; and a planarized insulator layer disposed between said at least partially exposed planar top metal layer and said at least one additional planar metal layer; wherein said at least partially exposed planar top metal layer is connected to said at least one additional planar metal layer by an electrically conductive via interconnect that extends through said planarized insulator layer between said at least partially exposed planar top metal layer and said at least one additional planar metal layer. 6. The infrared detector element of claim 5, wherein said ROIC comprises CMOS circuitry. 7. The infrared detector element of claim 5, wherein said at least partially exposed planar top metal layer is formed of a different material than said electrically conductive via interconnect. 8. The infrared detector element of claim 7, wherein said at least partially exposed planar top metal layer is formed of aluminum or alloy of aluminum; and wherein said electrically conductive via interconnect is formed of titanium tungsten or copper. 9. The infrared detector element of claim 1, wherein said ROIC is disposed on a first side of a substrate; wherein said microbolometer infrared radiation detector structure is disposed on said first side of said substrate; and wherein said ROIC further comprises: a first additional planar metal layer disposed between said at least partially exposed planar top metal layer and said substrate; a second additional planar metal layer disposed between said first additional planar metal layer and said at least partially exposed planar top metal layer; a first planarized insulator layer disposed between said first additional planar metal layer and said second additional planar metal layer; and a second planarized insulator layer disposed between said second additional planar metal layer and said at least partially exposed planar top metal layer; wherein said second additional planar metal layer is connected to said first additional planar metal layer by at least one first electrically conductive via interconnect that extends through said first planarized insulator layer between said second additional planar metal layer and said first additional planar metal layer; and wherein said at least partially exposed planar top metal layer is connected to said second additional planar metal layer by at least one second electrically conductive via interconnect that extends through said second planarized insulator layer between said at least partially exposed planar top metal layer and said second additional planar metal layer. 10. The infrared detector element of claim 9, wherein said ROIC comprises CMOS circuitry. 11. A focal plane array, comprising a plurality of infrared detector elements of claim 1. 12. The focal plane array of claim 11, wherein an exposed surface of said at least partially exposed planar top metal layer is substantially and continuously planar across said detector element. 13. A focal plane array assembly, comprising: a substrate having a first side; and a plurality of microbolometer infrared detector elements, each of said plurality of microbolometer infrared detector elements comprising a membrane suspended over said first side of said substrate and a lead metal reflector disposed on said first side of said substrate between said suspended membrane and said substrate; wherein said lead metal reflector for each of said microbolometer infrared detector elements comprises an at least partially exposed planar top metal layer of read out integrated circuitry (ROIC) that is configured as said lead metal reflector for said microbolometer infrared detector structure. 14. The focal plane array assembly of claim 13, wherein each of said plurality of microbolometer infrared detector elements further comprises at least one input pad for said ROIC, said input pad comprising a portion of said at least partially exposed planar top metal layer of said ROIC. 15. The focal plane array assembly of claim 13, wherein each of said microbolometer infrared detector elements comprises a diffractive resonant cavity (DRC) microbolometer structure. 16. The focal plane array assembly of claim 13, wherein said ROIC comprises CMOS circuitry; and wherein an at least partially exposed planar top metal layer of said CMOS circuitry is configured as said lead metal reflector for said microbolometer structure. 17. The focal plane array assembly of claim 13, wherein said ROIC further comprises: at least one additional planar metal layer disposed between said at least partially exposed planar top metal layer and said substrate; and a planarized insulator layer disposed between said at least partially exposed planar top metal layer and said at least one additional planar metal layer; wherein said at least partially exposed planar top metal layer is connected to said at least additional planar metal layer by an electrically conductive via interconnect that extends through said planarized insulator layer between said at least partially exposed planar top metal layer and said at least one additional planar metal layer. 18. The focal plane array assembly of claim 17, wherein said ROIC comprises CMOS circuitry. 19. The focal plane array assembly of claim 13, wherein said ROIC further comprises: a first additional planar metal layer disposed between said at least partially exposed planar top metal layer and said substrate; a second additional planar metal layer disposed between said first additional planar metal layer and said at least partially exposed planar top metal layer; a first planarized insulator layer disposed between said first additional planar metal layer and said second additional planar metal layer; and a second planarized insulator layer disposed between said second additional planar metal layer and said at least partially exposed planar top metal layer; wherein said second additional planar metal layer is connected to said first additional planar metal layer by at least one first electrically conductive via interconnect that extends through said first planarized insulator layer between said second additional planar metal layer and said first additional planar metal layer; and wherein said at least partially exposed planar top metal layer is connected to said second additional planar metal layer by at least one second electrically conductive via interconnect that extends through said second planarized insulator layer between said at least partially exposed planar top metal layer and said second additional planar metal layer. 20. The focal plane array assembly of claim 19, wherein said ROIC comprises CMOS circuitry. 21. The focal plane array assembly of claim 13, wherein an exposed surface of said at least partially exposed planar top metal layer is substantially and continuously planar across an array area of said focal plane array. 22. A wafer-level packaged focal plane array assembly, comprising: a device wafer, said device wafer comprising said substrate and said focal plane array assembly of claim 13; and a lid wafer, said lid wafer being at least partially transparent to infrared radiation and being assembled to said device wafer so that said lid wafer allows infrared radiation to reach said focal plane array assembly through said lid wafer. 23. The wafer-level packaged focal plane array assembly of claim 22, wherein said lid wafer is sealingly assembled to said device wafer and contains a vacuum therebetween to form a wafer-level packaged focal plane array assembly. 24. A method of making a focal plane array assembly, comprising: providing a substrate having a first side; forming a lead metal reflector on said first side of said substrate, said lead metal reflector comprising an at least partially exposed planar top metal layer of read out integrated circuitry (ROIC) with an at least partially exposed and reflective upper surface; and forming a plurality of membrane structures on said first side of said substrate so that each of said membrane structures is suspended over said first side of said substrate with said at least partially exposed planar top metal layer of said ROIC disposed between said suspended membrane and said substrate. 25. The method of claim 24, wherein each of said suspended membrane structures and said at least partially exposed planar top metal layer of said ROIC disposed between each of said suspended membrane structures and said substrate together comprise a microbolometer infrared detector element; and wherein said method further comprises forming at least one input pad for said ROIC of each of said microbolometer infrared detector elements, said input pad comprising a portion of said at least partially exposed planar top metal layer of said ROIC. 26. The method of claim 25, wherein each of said microbolometer infrared detector elements comprises a diffractive resonant cavity (DRC) microbolometer structure. 27. The method of claim 24, wherein said ROIC comprises CMOS circuitry; and wherein said method further comprises forming an at least partially exposed planar top metal layer of said CMOS circuitry as said lead metal reflector for said microbolometer structure. 28. The method of claim 24, wherein said step of forming said lead metal reflector on said first side of said substrate further comprises: forming at least one additional planar metal layer prior to forming said at least partially exposed planar top metal layer; forming a planarized insulator layer after forming said at least one additional planar metal layer and prior to forming said at least partially exposed planar top metal layer so that said at least one additional planar metal layer is disposed between said planarized insulator layer and said substrate; forming at least one electrically conductive via interconnect to extend through said planarized insulator layer and connect to said at least one additional planar metal layer; and forming said at least partially exposed planar top metal layer after forming said planarized insulator layer so that said planarized insulator layer is disposed between said at least partially exposed planar top metal layer and said at least one additional planar metal layer and so that said at least partially exposed planar top metal layer connects to said at least one electrically conductive via interconnect. 29. The method of claim 28, wherein said at least partially exposed planar top metal layer is a different material than said electrically conductive via interconnect. 30. The method of claim 29, wherein said at least partially exposed planar top metal layer is formed of aluminum or alloy of aluminum; and wherein said electrically conductive via interconnect is formed of titanium tungsten or copper. 31. The method of claim 28, further comprising forming said electrically conductive via interconnect during a first processing step, and forming said at least partially exposed planar top metal layer during a second processing step; wherein said first and second processing steps are different processing steps. 32. The method of claim 28, wherein said ROIC comprises CMOS circuitry. 33. The method of claim 24, wherein said step of forming said lead metal reflector on said first side of said substrate further comprises: forming a first additional planar metal layer prior to forming said at least partially exposed planar top metal layer; forming a second additional planar metal layer after forming said first additional planar metal layer and prior to forming said at least partially exposed planar top metal layer; forming a first planarized insulator layer having at least one first electrically conductive via interconnect extending therethrough after forming said first additional planar metal layer and prior to forming said second additional planar metal layer so that said first additional planar metal layer is disposed between said first planarized insulator layer and said substrate and so that said first and second additional planar metal layers are connected by said at least one first electrically conductive via interconnect; forming a second planarized insulator layer after forming said second additional planar metal layer and prior to forming said at least partially exposed planar top metal layer so that said second additional planar metal layer is disposed between said second planarized insulator layer and said first planarized insulator layer; forming at least one second electrically conductive via interconnect to extend through said second planarized insulator layer and connect to said second additional planar metal layer; and forming said at least partially exposed planar top metal layer after forming said second planarized insulator layer so that said second planarized insulator layer is disposed between said at least partially exposed planar top metal layer and said second additional planar metal layer and so that said at least partially exposed planar top metal layer connects to said at least one second electrically conductive via interconnect. 34. The method of claim 33, wherein said ROIC comprises CMOS circuitry. 35. The method of claim 24, further comprising planarizing an exposed surface of said at least partially exposed planar top metal layer to be substantially and continuously planar across an array area of said focal plane array. 36. A method of making a wafer-level packaged focal plane array assembly, comprising: providing a device wafer, said device wafer comprising said substrate and said focal plane array assembly of claim 24; providing a lid wafer, said lid wafer being at least partially transparent to infrared radiation; and assembling said lid wafer to said device wafer to form said wafer-level packaged focal plane array assembly, and so that said lid wafer allows infrared radiation to reach said focal plane array assembly through said lid wafer. 37. The method of claim 36, further comprising assembling and sealing said lid wafer to said device wafer in the presence of a vacuum so that a vacuum is sealingly contained between said lid wafer and said device wafer to form a wafer-level vacuum packaged focal plane array assembly.
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