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A method and apparatus for processing at least two types of payloads received at varying intervals in a communications network using a single processing path is provided. The two types of payloads may include virtually and contiguously concatenated payloads according to SONET/SHD architecture. The m

A method and apparatus for processing at least two types of payloads received at varying intervals in a communications network using a single processing path is provided. The two types of payloads may include virtually and contiguously concatenated payloads according to SONET/SHD architecture. The method comprises interleaving data in a predetermined format and controlling distribution of the data irrespective of the format received such that the data can be processed at the destination and passed to downstream components.

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What is claimed is: 1. A method for interleaving virtually concatenated and contiguously concatenated data, comprising: assigning a virtually concatenated data payload and a contiguously concatenated data payload to time slots in a received order in a first set of hardware data banks in a fiber opt

What is claimed is: 1. A method for interleaving virtually concatenated and contiguously concatenated data, comprising: assigning a virtually concatenated data payload and a contiguously concatenated data payload to time slots in a received order in a first set of hardware data banks in a fiber optics network, wherein the virtually concatenated data payload is variable in size to match a client service data rate, and wherein the contiguously concatenated data payload is fixed in size; and distributing the data from time slots in the received order in the first set of hardware banks to time slots in a generic order in a second set of hardware data banks such that contiguous data is included in each time slot; wherein said distributing is performed by a control memory and comprises determining a group format for the data, determining time slots to be employed based on the group format, and allocating data to only those time slots to be employed based on the group format. 2. The method of claim 1, wherein said assigning and distributing follow differential delay compensation for any virtually concatenated data. 3. The method of claim 1, wherein said assigning and distributing occur only if data is valid. 4. An apparatus for interleaving virtually concatenated and contiguously concatenated data irrespective of format received without substantially interrupting data flow, comprising: a plurality of memory buffers, each memory buffer holding a quantity of received data; and a plurality of control memories comprising a first control memory having an ability to select output data from the plurality of memory buffers within a fixed data boundary, and a second control memory having an ability to store a different configuration without interrupting operation of the first control memory, and an additional ability to switch functionality of the first control memory and the second control memory. 5. The apparatus of claim 4, further comprising a plurality of validity lines attached to the plurality of memory buffers, said validity lines indicating the validity of received data. 6. The apparatus of claim 4, wherein each memory buffer receives data over a predetermined size connection, and further comprising a plurality of reduction muxes, each reduction mux associated with one memory buffer, said reduction mux reducing the transmission from each memory buffer to a size value below said predetermined size. 7. The apparatus of claim 6, wherein said predetermined size is 64 bits, and each reduction mux reduces output to eight bits. 8. The apparatus of claim 4, wherein each memory buffer comprises a set of two identically sized memory elements, and wherein operation of said control memories operate to read from the memory elements. 9. The apparatus of claim 4, wherein the control memories distribute the data in time slots in accordance with an order received to time slots in a generic order such that contiguous data is included in each time slot, and further wherein said distributing comprises assessing data format and allocating data to time slots based on assessed data format. 10. The apparatus of claim 9, wherein the control memories distribute data from at least one time slot in the memory buffers in a specified order. 11. The apparatus of claim 4, wherein data received by said memory buffers is differential delay compensated for any received virtually concatenated data. 12. The apparatus of claim 5, wherein said data is received by the plurality of memory buffers only if data is valid. 13. A system comprising: a physical layer interface; a framer comprising: a plurality of memory buffers, each memory buffer holding a quantity of received data; and a plurality of control memories comprising a first control memory having an ability to select output data from the plurality of memory buffers within a fixed data boundary, and a second control memory having an ability to store a different configuration without interrupting operation of the first control memory, and an additional ability to switch functionality of the first control memory and the second control memory; a network processor; and an interface to at least provide intercommunication between the framer and the network processor. 14. The system of claim 13, wherein the interface is compatible with PCI. 15. The system of claim 13, wherein the interface is compatible with PCI-x. 16. The system of claim 13, further comprising a host-control plane controller coupled to the interface. 17. The system of claim 13, wherein the second interface is compatible with PCI. 18. The system of claim 13, wherein the second interface is compatible with PCI-x. 19. The system of claim 13, further comprising a second interface and a system fabric. 20. The system of claim 19, wherein the second interface is compatible with TFI-5. 21. The system of claim 19, wherein the second interface is compatible with CSIX. 22. The system of claim 19, further comprising a line card capable of intercommunicating with the system fabric. 23. The system of claim 22, wherein the line card is capable of providing an interface for a Fibre Channel compatible network. 24. The system of claim 22, wherein the line card is capable of providing an interface for an Ethernet compatible network. 25. The system of claim 22, wherein the line card is capable for performing add-drop multiplexing.