Video and graphics system with parallel processing of graphics windows
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-015/80
H04N-007/00
H04N-009/60
출원번호
UP-0485582
(2006-07-12)
등록번호
US-7659900
(2010-04-02)
발명자
/ 주소
MacInnis, Alexander G.
Tang, Chengfuh Jeffrey
Kranawetter, Greg A.
출원인 / 주소
Broadcom Corporation
대리인 / 주소
McAndrews, Held & Malloy, Ltd.
인용정보
피인용 횟수 :
7인용 특허 :
157
초록▼
A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple graphics layers, and the processing elements process two or more graphics layers in parallel to generate blended graphics. Alpha values may
A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple graphics layers, and the processing elements process two or more graphics layers in parallel to generate blended graphics. Alpha values may be used while blending graphics. The processing elements may be integrated on an integrated circuit chip with an input for receiving the graphics data and other video and graphics components. The display engine may also include a graphics controller for receiving two or more graphics layers in parallel, for arranging the graphics layers in an order suitable for parallel processing, and for providing the arranged graphics layers to the processing elements. The blended graphics may be blended with HDTV video or SDTV video, which may be extracted from compressed data streams such as an MPEG Transport stream.
대표청구항▼
What is claimed is: 1. A video and graphics system comprising: a plurality of graphics converters for receiving a plurality of graphics data portions, and for converting the graphics data portions to generate converted graphics data portions; a graphics controller for receiving the converted graphi
What is claimed is: 1. A video and graphics system comprising: a plurality of graphics converters for receiving a plurality of graphics data portions, and for converting the graphics data portions to generate converted graphics data portions; a graphics controller for receiving the converted graphics data portions and for ordering the converted graphics data portions into an order suitable for blending; and a plurality of graphics blenders for blending the converted graphics data portions concurrently to generate a blended graphics image. 2. The video and graphics system of claim 1, wherein the plurality of graphics data portions comprise a plurality of graphics windows. 3. The video and graphics system of claim 1, wherein the graphics blenders comprise at least two first level graphics blenders and at least one second level graphics blender, and wherein each of the first level graphics blenders blend at least two of the converted graphics data portions to generate one of intermediate graphics images, and the at least one second level graphics blender blends the intermediate graphics images to generate the blended graphics image. 4. The video and graphics system of claim 3, wherein the converted graphics data portions comprise at least two upper layer data portions and at least two lower layer data portions, wherein the at least two upper layer data portions are blended by a first one of the first level graphics blenders, and the at least two lower layer data portions are blended by a second one of the first level graphics blenders, wherein the at least two upper layer data portions are blended concurrently with the blending of the at least two lower layer data portions. 5. The video and graphics system of claim 1, wherein the graphics converters generate the converted graphics data portions having a common format. 6. The video and graphics system of claim 1, further comprising a plurality of CLUTs, each CLUT being coupled to a corresponding one of the graphics converters and being used for conversion of the graphics data portions having a CLUT data format. 7. The video and graphics system of claim 1, wherein the graphics converters, the graphics controller, and the graphics blenders are implemented on a single integrated circuit chip. 8. The video and graphics system of claim 1, wherein each of the converted graphics data portions represents a plurality of pixels and at least one blending factor, wherein the graphics blenders blend the converted graphics data portions using the at least one blending factor. 9. The video and graphics system of claim 1, further comprising a video compositor for receiving the blended graphics and a video, and for blending the blended graphics and the video using the at least one blending factor to generate a displayable image. 10. The video and graphics system of claim 9, the graphics converters, the graphics controller, the graphics blenders, and the video compositor are implemented on a single integrated circuit chip. 11. A method of blending a plurality of graphics data portions to generate a blended graphics image using a video and graphics system comprising a plurality of graphics converters, a graphics controller and a plurality of graphics blenders implemented on a single integrated circuit chip, the method comprising: converting the graphics data portions to a plurality of converted graphics data portions using the graphics converters; ordering the converted graphics data portions into an order suitable for blending using the graphics controller; and generating the blended graphics image by concurrently blending the converted graphics data portions using the graphics blenders. 12. The method of claim 11, wherein the plurality of graphics data portions comprise a plurality of graphics windows. 13. The method of claim 11, wherein generating the blended graphics image comprises blending at least two of the converted graphics data portions to generate a first one of intermediate graphics images, blending at least two other ones of the converted graphics data portions to generate a second one of the intermediate graphics images, and blending the intermediate graphics images to generate the blended graphics image. 14. The method of claim 13, wherein blending at least two of the converted graphics data portions comprises blending at least two upper layer data portions, and blending at least two other ones of the converted graphics data portions comprises blending at least two lower layer data portions, wherein the at least two upper layer data portions are blended concurrently with the blending of the at least two lower layer data portions. 15. The method of claim 11, wherein converting the graphics data portions comprises generating a plurality of converted graphics data portions having a common format. 16. The method of claim 11, wherein converting the graphics data portions comprises converting the graphics data portions having a CLUT data format using a plurality of CLUTs, each of the CLUTs corresponding to one of the graphics converters. 17. The method of claim 11, wherein each of the converted graphics data portions represents a plurality of pixels and at least one blending factor, wherein generating the blended graphics image comprises concurrently blending the converted graphics data portions using the at least one blending factor. 18. The method of claim 11, further comprising blending the blended graphics image and a video using at least one blending factor in a video compositor implemented on the single integrated circuit chip. 19. A video and graphics system comprising: conversion means for receiving the graphics data portions, and converting the graphics data portions to generate converted graphics data portions; ordering means for receiving the converted graphics data portions and ordering the converted graphics data portions into an order suitable for blending; and blending means for blending the converted graphics data portions concurrently to generate a blended graphics image. 20. The video and graphics system of claim 19, further comprising compositing means for blending the blended graphics image with a video to generate a displayable image.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (157)
Murphy Nicholas J. N.,GBX, 3D graphics object copying with reduced edge artifacts.
Cooper J. Carl (Monte Sereno CA) Wallen David (San Francisco CA) Vojnovic Mirko (Santa Clara CA) Loveless Howard (Ben Lomond CA), Apparatus and method for synchronizing asynchronous signals.
Drako Dean M. (Los Altos CA) Yu Hsiu-Tung A. (Palo Alto CA), Apparatus for manipulating image pixel streams to generate an output image pixel stream in response to a selected mode.
Clough Elizabeth A. (Menlo Park CA) Roskowski Steven G. (Sunnyvale CA) Perlman Stephen G. (Mountain View CA) Masterson Anthony D. (Cupertino CA), Apparatus for providing output filtering from a frame buffer storing both video and graphics signals.
Bates Cary L. (Rochester MN) Cragun Brian J. (Rochester MN) Donovan Robert J. (Rochester MN) Jaaskelainen William (Oronoco MN) Ryan Jeffrey M. (Byron MN) Striemer Bryan L. (Zumbrota MN), Aural position indicating mechanism for viewable objects.
Larson Michael Kerry ; McDonald Timothy James, Circuits systems and methods for managing data requests between memory subsystems operating in response to multiple address formats.
Gulick Dale ; Lambrecht Andy ; Webb Mike ; Hewitt Larry ; Barnes Brian, Computer system and method for transferring commands and data to a dedicated multimedia engine.
Mergard James Oliver ; Quimby Michael S. ; Wakeland Carl K., Computer system for concurrent data transferring between graphic controller and unified system memory and between CPU.
Gulick Dale E. ; Lambrecht Andy ; Webb Mike ; Hewitt Larry ; Barnes Brian, Computer system having a dedicated multimedia engine and multimedia memory having arbitration logic which grants main me.
Melo Maria L. ; Deschepper Todd ; Wilson Jeffrey T., Computer system having integrated bus bridge design with delayed transaction arbitration mechanism employed within laptop computer docked to expansion base.
Gulick Dale E. ; Lambrecht Andy ; Webb Mike ; Hewitt Larry ; Barnes Brian, Computer system having separate digital and analog system chips for improved performance.
Salbaum Helmut,DEX ; Bauer Harald,DEX ; Fruhwald Friedrich,DEX, D.M.A. controller that determines whether the mode of operation as either interrupt or D.M.A. via single control line.
Boyce Jill M. (Manalapan NJ) Pearlstein Larry (Newton PA), Digital video decoder for decoding digital high definition and/or digital standard definition television signals.
Werner Ross G. (Woodside CA) Ryherd Eric L. (Brookline NH), Drawing processor for computer graphic system using a plurality of parallel processors which each handle a group of disp.
Alexander G. MacInnis ; Chengfuh Jeffrey Tang ; Xiaodong Xie ; James T. Patterson ; Greg A. Kranawetter, Graphics display system with color look-up table loading mechanism.
MacInnis Alexander G. ; Tang Chengfuh Jeffrey ; Xie Xiaodong ; Patterson James T. ; Kranawetter Greg A., Graphics display system with unified memory architecture.
Van Hook Timothy J. ; Cheng Howard H. ; DeLaurier Anthony P. ; Gossett Carroll P. ; Moore Robert J. ; Shepard Stephen J. ; Anderson Harold S. ; Princen John ; Doughty Jeffrey C. ; Pooley Nathan F. ; , High performance low cost video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing.
Shibata Hideaki (Osaka JPX) Bannai Tatsushi (Sakai JPX), High-efficiency coding apparatus for compressing a digital video signal while controlling the coding bit rate of the com.
Lum Sanford S.,CAX ; Chen Keping,CAX ; Wong Samuel L. C.,CAX ; Bennett Dwayne R.,CAX ; Alford Michael A.,CAX, Host CPU independent video processing unit.
Borrel Paul ; Cheng Keh-Shin Fu ; Menon Jai Prakash ; Rossignac Jaroslaw Roman, Hotlinks between an annotation window and graphics window for interactive 3D graphics.
Miyuki Enokida JP; Tadashi Yoshida ; Kunihiro Yamamoto JP, Information processing method and apparatus for displaying a list of a plurality of image data files and a list of search results.
Rhodes Kenneth E. (Portland OR) Adams Robert T. (Lake Oswego OR) Janes Sherman (Portland OR) Coelho Rohan G. F. (Hillsboro OR), Integrated graphics and video computer display system.
Fandrianto Jan ; Martin Bryan R. ; Neubauer Doug G. ; Tran Duat H. ; Cressa Matthew D. ; Soemedi Arijanto, Integrated multimedia communications processor and codec.
Crochiere Ronald Eldon (Chatham NJ) Rabiner Lawrence Richard (Berkeley Heights NJ), Interpolation-decimation circuit for increasing or decreasing digital sampling frequency.
Nachtergaele Lode J.M.,BEX ; Catthoor Francky,BEX ; Kapoor Bhanu ; Janssens Stefan,BEX, Low power video decoder system with block-based motion compensation.
Carini Richard P. (Kingston NY) Donnelly James A. (West Hurley NY) Ellis ; Jr. Joseph J. (West Hurley NY) Lanzoni Thomas P. (Kingston NY), Merged data storage panel display.
Jouppi Norman P. ; McCormack Joel J. ; Chang Chun-Fa, Method and apparatus for compositing colors of images with memory constraints for storing pixel data.
Rhodes Ken (Portland OR) Coelho Rohan (Hillsboro OR) Frank Davis (Beaverton OR) Bender Blake (Beaverton OR), Method and apparatus for displaying an image in a windowed environment.
Gough Michael L. (Ben Lomond CA) Venolia Daniel S. (Foster City CA) Gilley Thomas S. (Pleasanton CA) Robbins Greg M. (Cupertino CA) Hansen ; Jr. Daniel J. (Cupertino CA) Oswal Abhay (Fremont CA) Tam , Method and apparatus for displaying an overlay image.
Dilliplane Stephen C. ; Lavelle Gary J. ; Maino James G. ; Selvaggi Richard J. ; Tseng Jack, Method and apparatus for displaying multiple windows on a display monitor.
Mills Karl Scott ; Holmes Jeffrey Michael ; Bonnelycke Mark Emil ; Owen Richard Charles Andrew, Method and apparatus for executing a raster operation in a graphics controller circuit.
Garrison John Michael ; Wilson Gale Arthur, Method and apparatus for manipulating very long lists of data displayed in a graphical user interface using a layered li.
Gough Michael L. ; MacDougald Joseph J. ; Venolia Daniel S. ; Gilley Thomas S. ; Robbins Greg M. ; Hansen ; Jr. Daniel J. ; Oswal Abhay, Method and apparatus for providing translucent images on a computer display.
Chow Paul,CAX ; Mizuyabu Carl K.,CAX ; Swan Philip L.,CAX ; Porter Allen J.C.,CAX ; Wang Chun,CAX, Method and apparatus for storing and displaying video image data in a video graphics system.
Yokota Teppei (Chiba JPX) Aramaki Junichi (Chiba JPX) Kihara Nobuyuki (Tokyo JPX), Method of recording on a recording medium employing an automatic updating of management data by monitoring the signal be.
King Sherman T. (San Francisco CA) Lee Tommy C. (Danville CA) Wang Niantsu (Milpitas CA) Chu Yen-Fah (San Jose CA) Kimura Scott A. (San Jose CA) Hwang Guorjuh T. (Milpitas CA), Multimedia overlay system for graphics and video.
Cottle Temple D. ; Spits Tiemen T., Programmable interrupt controller with interrupt set/reset register and dynamically alterable interrupt mask for a single interrupt processor.
Ogrinc Michael A. (San Francisco CA) Card Robert A. (Palo Alto CA) Burns Chris R. (Mountain View CA) Clarke Charles P. (Los Altos CA) Collier Ronda L. (Scotts Valley CA) Collins Kevin M. (San Mateo C, Real time video image processing system.
Slattery William ; Gratacap Regis, Remultipelxer cache architecture and memory organization for storing video program bearing transport packets and descriptors.
Fielder Dennis (Linton GBX) Derbyshire James (Willingham GBX) Gillingham Peter (Kanata CAX) Torrance Randy (Ottawa CAX) O\Connell Cormac (Kanata CAX), Single chip frame buffer and graphics accelerator.
Crinon Regis J. ; Sezan Muhammed Ibrahim, Sprite-based video coding system with automatic segmentation integrated into coding and sprite building processes.
Ke Ligang ; Lutz Juergen M., System and method for utilizing a two-dimensional adaptive filter for reducing flicker in interlaced television images converted from non-interlaced computer graphics data.
Priem Curtis ; Rosenthal David S. H., System for providing fast transfers to input/output device by assuring commands from only one application program reside in FIFO.
Washington Emanuel ; Perkins Mike ; Johnson Brian ; How Stephen ; Daines Nolan ; Ayers Tom ; Vertrees Keith, Transport stream decoder/demultiplexer for hierarchically organized audio-video streams.
Timothy J. Van Hook ; Howard H. Cheng ; Anthony P. DeLaurier ; Carroll P. Gossett ; Robert J. Moore ; Stephen J. Shepard ; Harold S. Anderson ; John Princen ; Jeffrey C. Doughty ; Nathan F. , Video game system and coprocessor for video game system.
Bae, Jong-Kon; Kim, Dokyung; Kim, Chulho; Park, Junho; Woo, Sooyoung; Cha, Chiho; Lee, Jeung Hwan, Display driver integrated circuit including first-in-first-out (FIFO) memories configured to receive display data from a distributor and output the display data to graphics memories a display system having the same, and a display data processing method thereof.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.