[특허]Single-clock, strobeless signaling system

[미국특허] Single-clock, strobeless signaling system 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G11C-008/02
출원번호	UP-0166248 (2008-07-01)
등록번호	US-7663966 (2010-04-04)
발명자 / 주소	Stark, Donald C.
출원인 / 주소	Rambus, Inc.
대리인 / 주소	Hunton & Williams, LLP
인용정보	피인용 횟수 : 1 인용 특허 : 174

초록 ▼

A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied

대표청구항 ▼

The invention claimed is: 1. A method of communicating information between a memory controller and a memory device, the method comprising: generating a first clock signal within the memory device, the first clock signal having a phase offset relative to a second clock signal that is determined at least in part by a signal propagation time on a signaling path between the memory device and the memory controller; transmitting information from the memory device to the memory controller under timing control of the first clock signal; generating a third clock signal within the memory device, the third clock signal having a phase offset relative to the second clock signal that is determined at least in part by the signal propagation time; and receiving information at the memory device from the memory controller under timing control of the third clock signal. 2. The method of claim 1, wherein generating a third clock signal comprises generating a third clock signal that leads the first clock signal by a phase offset that is determined at least in part by the signal propagation time. 3. The method of claim 1, wherein the first and third clock signals have a higher frequency than the second clock signal. 4. The method of claim 1, wherein the phase offset of the first clock signal relative to the second clock signal is further determined at least in part by a value stored in a phase offset register in the memory device. 5. The method of claim 4, further comprising receiving the value at the memory device from the memory controller for storage in the phase offset register in the memory device. 6. The method of claim 4, further comprising transmitting the value from the memory controller to the memory device for storage in the phase offset register in the memory device. 7. The method of claim 4, further comprising receiving a command at the memory device from the memory controller via the signaling path instructing the memory device to adjust the value in the phase offset register in the memory device. 8. The method of claim 4, further comprising transmitting a command from the memory controller to the memory device instructing the memory device to adjust the value in the phase offset register in the memory device. 9. The method of claim 4, further comprising transmitting a predetermined sequence of bits from the memory device to the memory controller via the signaling path in a calibration operation to determine the value stored in the phase offset register in the memory device. 10. The method of claim 9, further comprising receiving the predetermined sequence of bits at the memory device from the memory controller via the signaling path for later transmission from the memory device to the memory controller via the signaling path in the calibration operation. 11. The method of claim 10, wherein the predetermined sequence of bits is received at the memory device from the memory controller with a calibration command. 12. The method of claim 9, further comprising transmitting the predetermined sequence of bits from the memory controller to the memory device via the signaling path for later transmission from the memory device to the memory controller via the signaling path in the calibration operation. 13. The method of claim 12, wherein the predetermined sequence of bits is transmitted from the memory controller to the memory device with a calibration command. 14. The method of claim 1, wherein the phase offset of the third clock signal relative to the second clock signal is further determined at least in part by a value stored in a phase offset register in the memory device. 15. The method of claim 14, further comprising receiving the value at the memory device from the memory controller for storage in the phase offset register in the memory device. 16. The method of claim 14, further comprising transmitting the value from the memory controller to the memory device for storage in the phase offset register in the memory device. 17. The method of claim 14, further comprising receiving a command at the memory device from the memory controller via the signaling path instructing the memory device to adjust the value in the phase offset register in the memory device. 18. The method of claim 14, further comprising transmitting a command from the memory controller to the memory device instructing the memory device to adjust the value in the phase offset register in the memory device. 19. The method of claim 14, further comprising receiving a predetermined sequence of bits at the memory device from the memory controller via the signaling path in a calibration operation to determine the value stored in the phase offset register in the memory device. 20. The method of claim 19, wherein the predetermined sequence of bits is received at the memory device from the memory controller with a calibration command. 21. The method of claim 19, further comprising transmitting the received predetermined sequence of bits from the memory device to the memory controller via the signaling path. 22. The method of claim 14, further comprising transmitting a predetermined sequence of bits from the memory controller to the memory device via the signaling path in a calibration operation to determine the value stored in the phase offset register in the memory device. 23. The method of claim 22, wherein the predetermined sequence of bits is transmitted from the memory controller to the memory device with a calibration command. 24. The method of claim 22, further comprising transmitting the transmitted predetermined sequence of bits from the memory device to the memory controller via the signaling path.

이 특허에 인용된 특허 (174) 인용/피인용 타임라인 분석

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Harrison Ronnie M. ; Keeth Brent, Synchronous clock generator including a compound delay-locked loop.
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Harrison Ronnie M., Synchronous clock generator including a false lock detector.
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Harrison Ronnie M. ; Keeth Brent, Synchronous clock generator including delay-locked loop.
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Garlepp, Bruno Werner; Chau, Pak Shing; Donnelly, Kevin S.; Portmann, Clemenz; Stark, Donald C.; Sidiropoulos, Stefanos; Barth, Richard M.; Davis, Paul G.; Tsern, Ely K., Synchronous memory device having a temperature register.
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Read James F. ; Moore Leonard W., System and method for synchronizing clocks in a plurality of devices across a communication channel.
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Wendte Keith W., System for analyzing spatially-variable harvest data by pass.
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Vogley Wilbur C. (Missouri City TX), Time skewing arrangement for operating memory in synchronism with a data processor.
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Heller Lawrence D. (Watertown MA), Transmitting electrical signals with a transmission time independent of distance between transmitter and receiver.
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Stark, Donald C., Single-clock, strobeless signaling system.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

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[미국특허] Single-clock, strobeless signaling system 원문보기

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이 특허에 인용된 특허 (174) 인용/피인용 타임라인 분석

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