최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | UP-0205716 (2005-08-17) |
등록번호 | US-7668017 (2010-04-09) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 1 인용 특허 : 491 |
A method includes determining groups of rows to erase together in order to minimize the margin loss associated with bake after a large number of program and erasure cycles. The method alternatively includes determining groups of rows to erase together to minimize the width of a resultant erase thres
A method includes determining groups of rows to erase together in order to minimize the margin loss associated with bake after a large number of program and erasure cycles. The method alternatively includes determining groups of rows to erase together to minimize the width of a resultant erase threshold voltage distribution, erasing the groups together, stopping erasure of a group when the group is erase verified and performing the step of erasing on those groups which were not previously erase verified.
What is claimed is: 1. A non-volatile memory chip comprising: a memory array of non-volatile memory cells formed into rows and columns; a logic circuit adapted to determine groups of rows to erase together; an X decoder to activate a row of said memory array; and an erase flag register to identify
What is claimed is: 1. A non-volatile memory chip comprising: a memory array of non-volatile memory cells formed into rows and columns; a logic circuit adapted to determine groups of rows to erase together; an X decoder to activate a row of said memory array; and an erase flag register to identify groups of said rows to erase together. 2. The chip according to claim 1 and wherein each said group is a set of M consecutive rows. 3. The chip according to claim 1 and wherein each said group is a set of N rows aligned with a non-uniformity in said array. 4. The chip according to claim 1 and wherein each said group is a set of A rows aligned with a non-uniformity in programming speed of the array cells during program operation. 5. The chip according to claim 1 and wherein each said group is a set of B rows aligned with a non-uniformity in erase speed of the array cells during erase operation. 6. The chip according to claim 1 and wherein each said group is a set of C rows aligned with a non-uniformity in the distance of a row from a strapping location for said row. 7. The chip according to claim 1 and wherein each said group is a set of D rows which erased within the same number of pulses during a previous erase operation. 8. A method comprising: determining groups of rows to erase together to minimize the width of a resultant erase threshold voltage distribution; erasing said groups together; stopping erasure of a group when said group is erase verified; and performing said step of erasing on those groups which were not previously erase verified. 9. The method according to claim 8 and wherein each said group is a set of M consecutive rows. 10. The method according to claim 8 and wherein each said group is a set of N rows aligned with the array non-uniformity. 11. The method according to claim 8 and wherein each said group is a set of A rows aligned with a non-uniformity in programming level and speed of the array cells during program operation. 12. The method according to claim 8 and wherein each said group is a set of B rows aligned with a non-uniformity in erase speed of the array cells during erase operation. 13. The method according to claim 8 and wherein each said group is a set of C rows defined by the distance of a row from a strapping location for said row. 14. The method according to claim 8 and wherein each said group is a set of D rows which erased within the same number of pulses during a previous erase operation. 15. A method comprising: determining groups of rows to erase together in order to minimize the margin loss associated with bake resulting from multiple program and erasure cycles. 16. The method according to claim 15 and wherein each said group is a set of M consecutive rows. 17. The method according to claim 15 and wherein each said group is a set of N rows aligned with the array non-uniformity. 18. The method according to claim 15 and wherein each said group is a set of A rows aligned with a non-uniformity in programming level and speed of the array cells during program operation. 19. The method according to claim 15 and wherein each said group is a set of B rows aligned with a non-uniformity in erase speed of the array cells during erase operation. 20. The method according to claim 15 and wherein each said group is a set of C rows defined by the distance of a row from a strapping location for said row. 21. The method according to claim 15 and wherein each said group is a set of D rows which erased within the same number of pulses during a previous erase operation.
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