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Techniques of ripple reduction for charge pumps 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G05F-001/10
출원번호 UP-0146243 (2008-06-25)
등록번호 US-7683700 (2010-04-21)
발명자 / 주소
  • Huynh, Jonathan H.
  • Nguyen, Qui Vi
  • Pang, Feng
출원인 / 주소
  • SanDisk Corporation
대리인 / 주소
    Davis Wright Tremaine LLP
인용정보 피인용 횟수 : 29  인용 특허 : 67

초록

A charge pump system for supplying an output voltage to a load is described. It includes a regulation circuit connected to receive the output voltage and derive an enable signal from it and multiple charge pump circuits connected in parallel to supply the output voltage. Each of the charge pump circ

대표청구항

It is claimed: 1. A charge pump system for supplying an output voltage to a load, comprising: a regulation circuit connected to receive the output voltage and derive an enable signal therefrom; a plurality of charge pump circuits connected in parallel to supply the output voltage, each of the charg

이 특허에 인용된 특허 (67)

  1. Haeberli, Andreas M.; Wong, Sau C.; So, Hock C.; Werner, Carl W.; Wang, Cheng-Yuan Michael; Wong, Leon Sea Jiunn, Adjustable circuits for analog or multi-level memory.
  2. Collins,Michael John; Frank,Richard, Apparatus and method for charge pump control with adjustable series resistance.
  3. Li, Bo, Apparatus and method to read a nonvolatile memory.
  4. Cernea, Raul-Adrian, Area efficient charge pump.
  5. Cernea,Raul Adrian, Area efficient charge pump.
  6. Tsukada Shyuichi (Tokyo JPX), Boost voltage generating circuit.
  7. Tanimoto, Takashi, Booster and imaging device using booster.
  8. Kotowski Jeff ; McIntyre William J., Buck and boost switched capacitor gain stage with optional shared rest state.
  9. Kowshik Vikram (Fremont CA) Yu Andy Teng-Feng (Palo Alto CA), Charge pump.
  10. Johnson, Mark G.; Nolan, III, Joseph G.; Crowley, Matthew P., Charge pump circuit.
  11. Andreas M. Haeberli ; Sau C. Wong ; Hock C. So ; Carl W. Werner ; Cheng-Yuan Michael Wang ; Leon Sea Jiunn Wong, Charge pump circuit adjustable in response to an external voltage source.
  12. Haeberli, Andreas M.; Wong, Sau C.; So, Hock C.; Werner, Carl W.; Wang, Cheng-Yuan Michael; Wong, Leon Sea Jiunn, Charge pump circuit adjustable in response to an external voltage source.
  13. Le Binh Quang ; Chen Pau-Ling ; Hollmer Shane, Charge pump circuit architecture.
  14. Cini Carlo (Cornaredo ITX) Diazzi Claudio (Milan ITX) Rossi Domenico (Cilavegna ITX), Charge pump circuit for driving N-channel MOS transistors.
  15. Thorp,Tyler J.; Scheuerlein,Roy E., Charge pump circuit incorporating corresponding parallel charge pump stages and method therefor.
  16. Cernea Raul-Adrian (Cupertino CA), Charge pump circuit with exponetral multiplication.
  17. Gupta Anil (Sunnyvale CA), Charge pump for providing programming voltage to the word lines in a semiconductor memory array.
  18. Latham ; II Paul W. (Marlboro MA), Charge pump for use in a phase-locked loop.
  19. Cernea,Raul Adrian, Charge pump with fibonacci number multiplication.
  20. Takao Myono JP, Charge-pump circuit and control method thereof.
  21. Viehmann Hans-Heinrich,DEX, Circuit configuration for supplying an electronic load circuit.
  22. Chevallier Christophe J. ; Lakhani Vinod C., Clocking scheme and charge transfer switch for increasing the efficiency of a charge pump or other circuit.
  23. Yuji Segawa JP; Masaru Otsuka JP; Osamu Kikuchi JP; Akira Haga JP; Yoshinori Yoshikawa JP, Comparator and voltage controlled oscillator circuit.
  24. Nicholson, Richard; Churchill, Simon, Continuous linear regulated zero dropout charge pump with high efficiency load predictive clocking scheme.
  25. Wong Ting-Wah (San Jose CA) Cernea Raul-Adrian (Walnut Creek CA), Current-regulated, voltage-regulated erase circuit for EEPROM memory.
  26. Oshio, Umeo, DC-DC converter and storage apparatus.
  27. Van Buskirk Michael A. (San Jose CA) Chen Johnny C. (Cupertino CA) Chang Chung K. (Sunnyvale CA) Cleveland Lee E. (Santa Clara CA) Montalvo Antonio (Raleigh NC), Drain power supply.
  28. Lee Jong Seuk,KRX, Drain voltage pumping circuit.
  29. Cernea Raul-Adrian (Santa Clara CA) Lee Douglas J. (San Jose CA) Mofidi Mehrdad (Fremont CA) Mehrotra Sanjay (Milpitas CA), Flash EEPROM self-adaptive voltage generation circuit operative within a continuous voltage source range.
  30. Pan,Feng; Pham,Trung, Four phase charge pump operable without phase overlap with improved efficiency.
  31. Wong Sau C., High data rate write process for non-volatile flash memories.
  32. Wong Sau C., High data rate write process for non-volatile flash memories.
  33. Wong, Sau C., High data rate write process for non-volatile flash memories.
  34. Wong, Sau C., High data rate write process for non-volatile flash memories.
  35. Gariboldi, Roberto; Lavorerio, Riccardo; Sala, Leonardo; Nidasio, Giovanni, High efficiency electronic circuit for generating and regulating a supply voltage.
  36. Kyung Kye-Hyun,KRX, High voltage generating circuit for a semiconductor memory device.
  37. Pan, Feng, High voltage ripple reduction.
  38. Pan,Feng, High voltage ripple reduction and substrate protection.
  39. Kirsch Howard C. (Emmaus PA) Stefany James H. (Asbury NJ), Integrated circuit having a variably boosted node.
  40. Koji Hosono JP; Yasuo Itoh JP; Ken Takeuchi JP, Internal voltage generating circuit capable of generating variable multi-level voltages.
  41. Cave Michael D. (Pflugerville TX) Zavaleta Mauricio A. (Austin TX), Method and apparatus for a regulated supply on an integrated circuit.
  42. Pasternak, John H., Method and system for distributed power generation in multi-chip memory systems.
  43. Koh Han Young ; Tuan Jeh-Fu ; Young Tak K., Method and system for reliability analysis of CMOS VLSI circuits based on stage partitioning and node activities.
  44. Ciro W. Milazzo, Method for sensing the output voltage of a charge pump circuit without applying a load to the output stage.
  45. Binh Q. Le ; Pau-Ling Chen, Modulated charge pump with uses an analog to digital converter to compensate for supply voltage variations.
  46. Bendik Kleveland, Multi-stage charge pump.
  47. Myono, Takao, Multi-stage switched capacitor DC-DC converter.
  48. Gorobets,Sergey Anatolievich; Li,Yan, Pipelined programming of non-volatile memories using early data.
  49. Cernea Raul-Ardian (Cupertino CA) Lee Douglas J. (San Jose CA) Mofidi Mehrdad (Fremont CA) Mehrotra Sanjay (Milpitas CA), Process for manufacturing a programmable power generation circuit for flash EEPROM memory systems.
  50. Cernea Raul-Adrian (Cupertino CA) Lee Douglas J. (San Jose CA) Mofidi Mehrdad (Fremont CA) Mehrotra Sanjay (Milpitas CA), Programmable power generation circuit for flash EEPROM memory systems.
  51. Cernea Raul-Adrian (Cupertino CA) Lee Douglas J. (San Jose CA) Mofidi Mehrdad (Fremont CA) Mehrotra Sanjay (Milpitas CA), Programmable power generation circuit for flash EEPROM memory systems.
  52. Cernea Raul-Adrian (Cupertino CA) Lee Douglas J. (San Jose CA) Mofidi Mehrdad (Fremont CA) Mehrotra Sanjay (Milpitas CA), Programmable power generation circuit for flash EEPROM memory systems.
  53. Cernea Raul-Adrian (Cupertino CA) Lee Douglas J. (San Jose CA) Mofidi Mehrdad (Fremont CA) Mehrotra Sanjay (Milpitas CA), Programmable power generation circuit for flash EEPROM memory systems.
  54. Cernea Raul-Adrian (Cupertino CA) Lee Douglas J. (San Jose CA) Mofidi Mehrdad (Fremont CA) Mehrotra Sanjay (Milpitas CA), Programmable power generation circuit for flash eeprom memory systems.
  55. Jin Seung Eon,KRX, Pumping circuit with amplitude limited to prevent an over pumping for semiconductor device.
  56. Zavaleta Mauricio A. (Austin TX), Regulated charge pump and method therefor.
  57. Tailliet,Fran?ois, Self-reparable device to generate a high voltage, and method for repairing a device to generate a high voltage.
  58. Haraguchi Masaru,JPX ; Yamasaki Kyoji,JPX ; Nakaoka Yoshito,JPX, Semiconductor device.
  59. Komori,Hideki; Kawamura,Shouichi; Taya,Masanori, Semiconductor device and control method thereof.
  60. Matano Tatsuya,JPX, Semiconductor device with less influence of noise.
  61. Hashimoto,Takeshi; Ito,Yutaka, Semiconductor memory device control method and semiconductor memory device.
  62. Bui, John H., Universally programmable output buffer.
  63. Bedarida, Lorenzo; Bartoli, Simone; Sivero, Stefano, Variable charge pump circuit with dynamic load.
  64. Naganawa Koji,JPX, Voltage booster circuit.
  65. Kiyoshi Miyazaki JP, Voltage multiplier having an intermediate tap.
  66. Camacho Stephen ; Walker Robert ; Lao Tim, Voltage pump for integrated circuit and operating method thereof.
  67. Peschke,Carlo Eberhard, Voltage regulated charge pump with regulated charge current into the flying capacitor.

이 특허를 인용한 특허 (29)

  1. Sabde, Jagdish; Magia, Sagar; Pachamuthu, Jayavel, AC stress methods to screen out bit line defects.
  2. Magia, Sagar; Sabde, Jagdish, AC stress mode to screen out word line to word line shorts.
  3. Jeong, Young Kyun; Jang, Young Tae; Koh, Kyoung Min, Boost circuit capable of controlling inrush current and image sensor using the boost circuit.
  4. Pan, Feng; Wang, Jun; Guhados, Shankar; Lei, Bo, Charge pump based over-sampling ADC for current detection.
  5. Huynh, Jonathan; Pham, Trung; Wang, Sung-en; Park, Jongmin, Charge pump based over-sampling with uniform step size for current detection.
  6. Cook, Thomas D.; Cunningham, Jeffrey C.; Ramanan, Karthik, Charge pump for use with a synchronous load.
  7. Huynh, Jonathan; Wang, Sung-En; Park, Jongmin, Charge pump strength calibration and screening in circuit design.
  8. Sharon, Eran; Li, Yan; Lee, Dana; Alrod, Idan, Combined simultaneous sensing of multiple wordlines in a post-write read (PWR) and detection of NAND failures.
  9. Sharon, Eran; Alrod, Idan, Data recovery for defective word lines during programming of non-volatile memory arrays.
  10. Kochar, Mrinal; Huang, Jianmin; Wan, Jun, Detection of broken word-lines in memory arrays.
  11. Shah, Grishma Shailesh; Li, Yan, Detection of broken word-lines in memory arrays.
  12. Li, Yan; Lee, Dana; Huynh, Jonathan, Detection of word-line leakage in memory arrays.
  13. Sbade, Jagdish M.; Magia, Sagar, Determination of bit line to low voltage signal shorts.
  14. Magia, Sagar; Sabde, Jagdish M., Determination of word line to local source line shorts.
  15. Magia, Sagar; Sabde, Jagdish; Nguyen, Khanh, Determination of word line to word line shorts between adjacent blocks.
  16. Sabde, Jagdish; Magia, Sagar; Nguyen, Khanh, Determination of word line to word line shorts between adjacent blocks.
  17. Reddy, Gooty Sukumar; Kumar, Potnuru Venkata Pradeep; Yadala, Sridhar, Dynamic clock period modulation scheme for variable charge pump load currents.
  18. Yang, Niles Nian; Avila, Chris, Dynamic memory recovery at the sub-block level.
  19. Reddy, Gooty Sukumar; Kumar, Potnuru Venkata Pradeep; Yadala, Sridhar, High voltage generation using low voltage devices.
  20. Tam, Eugene Jinglun, Multi-word line erratic programming detection.
  21. Sharon, Eran, Non-volatile memory and method with accelerated post-write read using combined verification of multiple pages.
  22. Paudel, Rajan; Sabde, Jagdish; Magia, Sagar; Nguyen, Khanh, Non-volatile memory with multi-word line select for defect detection operations.
  23. Terçariol, Walter L.; Saez, Richard Titov Lara; Salvarani, Alfredo; Kickhofel, Remerson Stein, Reducing output voltage ripple of power supplies.
  24. Koh, Pao-Ling; Kuo, Tien-Chien, Saving of data in cases of word-line to word-line short in memory arrays.
  25. Reddy, Gooty Sukumar; Yadala, Sridhar, Selective body bias for charge pump transfer switches.
  26. Park, Minsang, Semiconductor memory device for diminishing peak current in multi-die memory structure.
  27. Pan, Feng; Guhados, Shankar, Sigma delta over-sampling charge pump analog-to-digital converter.
  28. Sharon, Eran; Li, Yan; Lee, Dana; Alrod, Idan, Simultaneous sensing of multiple wordlines and detection of NAND failures.
  29. Magia, Sagar; Sabde, Jagdish; Kuo, Tien-Chien; Pachamuthu, Jayavel, Techniques for detecting broken word lines in non-volatile memories.
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