[특허]Stacked integrated circuit package system and method of manufacture therefor

[미국특허] Stacked integrated circuit package system and method of manufacture therefor 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/00 H01L-023/02 H05K-007/00
출원번호	UP-0045606 (2008-03-10)
등록번호	US-7687315 (2010-04-23)
발명자 / 주소	Carson, Flynn
출원인 / 주소	STATS ChipPAC Ltd.
대리인 / 주소	Ishimaru, Mikio
인용정보	피인용 횟수 : 5 인용 특허 : 209

초록 ▼

An integrated circuit package system including providing a base substrate, attaching a base integrated circuit on the base substrate, attaching a core substrate over the base integrated circuit, attaching a substrate electrical connector between the core substrate and the base substrate, and applyin

대표청구항 ▼

What is claimed is: 1. A method of manufacture of an integrated circuit package system comprising: providing a base substrate; attaching a base integrated circuit over the base substrate; attaching a core substrate over the base integrated circuit, the core substrate and a core substrate connection having sides facing the base substrate partially exposed from an attachment layer on the core substrate and the base integrated circuit; attaching a substrate electrical connector between the core substrate and the base substrate; and applying an encapsulant directly on a perimeter portion of a side of the core substrate opposite the base substrate and having a center portion of the side of the core substrate substantially exposed over the base integrated circuit. 2. The method as claimed in claim 1 further comprising attaching a top integrated circuit on a mounting surface of the core substrate. 3. The method as claimed in claim 1 wherein attaching the base integrated circuit comprises attaching a solder ball or a bond wire between the base integrated circuit and the base substrate. 4. The method as claimed in claim 1 wherein attaching the base integrated circuit comprises attaching another integrated circuit adjacent the base integrated circuit. 5. The method as claimed in claim 1 wherein attaching the base integrated circuit comprises attaching a base electrical connector over the base integrated circuit and part of the base substrate. 6. A method of manufacture of an integrated circuit package system comprising: forming a base substrate having a base connection pad; connecting a base integrated circuit with a base electrical connector over the base substrate; attaching a core substrate on an attachment layer on the base integrated circuit, the core substrate and a core substrate connection having sides facing the base substrate partially exposed from the attachment layer; connecting a substrate electrical connector between the core substrate and the base substrate; forming an encapsulant over a perimeter portion at an edge of the mounting surface of the core substrate having a core connection pad exposed in a center portion of the mounting surface over the base integrated circuit; and connecting a top electrical connector between a top integrated circuit and the core connection pad. 7. The method as claimed in claim 6 wherein connecting the base integrated circuit comprises attaching a bond wire between another integrated circuit on the base integrated circuit and the base substrate. 8. The method as claimed in claim 6 wherein connecting the base integrated circuit comprises attaching a flipchip on the base integrated circuit. 9. The method as claimed in claim 6 wherein forming the encapsulant comprises forming a mounting surface on the core substrate for a top integrated circuit. 10. The method as claimed in claim 6 wherein attaching the core substrate comprises providing the core substrate with lower routing density than routing density of the base substrate. 11. An integrated circuit package system comprising: a base substrate; a base integrated circuit over the base substrate; a core substrate having a core substrate connection over the base integrated circuit; an attachment layer on the core substrate and the base integrated circuit, the core substrate and the core substrate connection having sides facing the base substrate partially exposed from the attachment layer; a substrate electrical connector between the core substrate and the base substrate; and an encapsulant directly on a perimeter portion of a side of the core substrate opposite the base substrate and having a portion of the side of the core substrate substantially exposed over the base integrated circuit. 12. The system as claimed in claim 11 further comprising a top integrated circuit on a mounting surface of the core substrate. 13. The system as claimed in claim 11 further comprising a solder ball or a bond wire between the base integrated circuit and the base substrate. 14. The system as claimed in claim 11 further comprising another integrated circuit adjacent the base integrated circuit. 15. The system as claimed in claim 11 further comprising a base electrical connector over the base integrated circuit and part of the base substrate. 16. The system as claimed in claim 11 wherein: the base substrate having a base connection pad; the base integrated circuit with a base electrical connector over the base substrate; the core substrate on an attachment layer over the base integrated circuit; the substrate electrical connector between the core substrate and the base substrate; the encapsulant over the core substrate having a core connection pad exposed over the base integrated circuit; and further comprising: a top electrical connector between a top integrated circuit and the core connection pad. 17. The system as claimed in claim 16 further comprising a bond wire between another integrated circuit on the base integrated circuit and the base substrate. 18. The system as claimed in claim 16 further comprising a flipchip on the base integrated circuit. 19. The system as claimed in claim 16 wherein the encapsulant comprises a mounting surface on the core substrate for a top integrated circuit. 20. The system as claimed in claim 16 wherein the core substrate comprises lower routing density than routing density of the base substrate.

이 특허에 인용된 특허 (209) 인용/피인용 타임라인 분석

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

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