[특허]Wafer-level burn-in and test

[미국특허] Wafer-level burn-in and test 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G01R-031/02 G01R-031/26
출원번호	UP-0050857 (2008-03-18)
등록번호	US-7688090 (2010-04-23)
발명자 / 주소	Khandros, Igor Y. Pedersen, David V.
출원인 / 주소	FormFactor, Inc.
대리인 / 주소	Burraston, N. Kenneth
인용정보	피인용 횟수 : 1 인용 특허 : 94

초록 ▼

Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. A significant reduction in interconnect count and consequent simplification of the interconnection substrate is realized because the ASICs are capable of receiving a plurality of signals for testing the DUTs over relatively few signal lines from a host controller and promulgating these signals over the relatively many interconnections between the ASICs and the DUTs. The ASICs can also generate at least a portion of these signals in response to control signals from the host controller. Physical alignment techniques are also described. Micromachined indentations on the front surface of the ASICs ensure capturing free ends of the spring contact elements. Micromachined features on the back surface of the ASICs and the front surface of the interconnection substrate to which they are mounted facilitate precise alignment of a plurality of ASICs on the support substrate.

대표청구항 ▼

What is claimed is: 1. A method of testing an electronic device comprising: providing a test apparatus comprising a plurality of first contacts disposed on integrated circuits of the test apparatus and a serial interface coupled to the integrated circuits; coupling the serial interface to a tester; bringing the test apparatus and a device under test together to form temporary electrical connections between ones of the first contacts and corresponding ones of second contacts of the device under test; communicating test data from the tester to the plurality of integrated circuits via the serial interface; generating a plurality of test vectors in response to the test data using the integrated circuits; and transmitting a plurality of the test vectors to the device under test via the temporary electrical connections, wherein the communicating test data uses a first number of electrical connections of the serial interface and wherein the transmitting a plurality of test vectors uses a second number of the temporary electrical connections, and the first number is substantially less than the second number. 2. The method of claim 1, further comprising: receiving a response from the device under test via the temporary electrical connections; comparing the response to at least a portion of the plurality of test vectors using the integrated circuits; and communicating a result back to the tester via the serial interface. 3. A method of testing an electronic device comprising: providing a test apparatus comprising a plurality of first contacts disposed on integrated circuits of the test apparatus and a serial interface coupled to the integrated circuits; coupling the serial interface to a tester; bringing the test apparatus and a device under test together to form temporary electrical connections between ones of the first contacts and corresponding ones of second contacts of the device under test; communicating test data from the tester to the plurality of integrated circuits via the serial interface; generating a plurality of test vectors in response to the test data using the integrated circuits; and transmitting a plurality of the test vectors to the device under test via the temporary electrical connections, wherein the generating a plurality of test vectors comprises algorithmically generating addresses and data values for memory testing of the device under test. 4. A probe card assembly for testing an electronic device comprising: means for forming a first number of temporary electrical connections with a device under test; means for receiving test signals from a tester through a second number of electrical connections, the second number being substantially less than the first number; means for generating test vectors based on the test signals; and means for applying the test vectors to the device under test via ones of the first number of temporary electrical connections. 5. The probe card assembly of claim 4, further comprising means for receiving response vectors from the device under test via ones of the first number of temporary electrical connections; means for comparing the response vectors to at least a portion of the test vectors to determine a test result; and means for communicating the test result to the tester via the second number of electrical connections. 6. The probe card assembly of claim 4, wherein the means for generating test vectors comprises a means for generating memory pattern tests. 7. The probe card assembly of claim 4, wherein: the test vectors comprise addresses and data values for memory testing of the device under test, and the means for generating generates the addresses and the data values algorithmically. 8. The probe card assembly of claim 7, wherein the means for forming comprises a plurality of electrically conductive contacts. 9. The probe card assembly of claim 4, wherein the means for receiving receives the test signals serially.

이 특허에 인용된 특허 (94) 인용/피인용 타임라인 분석

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[미국특허] Wafer-level burn-in and test 원문보기

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이 특허에 인용된 특허 (94) 인용/피인용 타임라인 분석

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