Balancing computational load across a plurality of processors
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-009/46
G06F-009/44
G06F-009/45
출원번호
UP-0145709
(2008-06-25)
등록번호
US-7694306
(2010-05-20)
발명자
/ 주소
Minor, Barry L
Nutter, Mark Richard
To, VanDung Dang
출원인 / 주소
International Business Machines Corporation
대리인 / 주소
VanLeeuwen & VanLeeuwen
인용정보
피인용 횟수 :
11인용 특허 :
88
초록▼
Computational load is balanced across a plurality of processors. Source code subtasks are compiled into byte code subtasks whereby the byte code subtasks are translated into processor-specific object code subtasks at runtime. The processor-type selection is based upon one of three approaches which a
Computational load is balanced across a plurality of processors. Source code subtasks are compiled into byte code subtasks whereby the byte code subtasks are translated into processor-specific object code subtasks at runtime. The processor-type selection is based upon one of three approaches which are 1) a brute force approach, 2) higher-level approach, or 3) processor availability approach. Each object code subtask is loaded in a corresponding processor type for execution. In one embodiment, a compiler stores a pointer in a byte code file that references the location of a byte code subtask. In this embodiment, the byte code subtask is stored in a shared library and, at runtime, a runtime loader uses the pointer to identify the location of the byte code subtask in order to translate the byte code subtask.
대표청구항▼
What is claimed is: 1. An information handling system comprising: a plurality of heterogeneous processors, each of the heterogeneous processors corresponding to one of a plurality of heterogeneous processor types; a memory accessible by the heterogeneous processors; one or more nonvolatile storage
What is claimed is: 1. An information handling system comprising: a plurality of heterogeneous processors, each of the heterogeneous processors corresponding to one of a plurality of heterogeneous processor types; a memory accessible by the heterogeneous processors; one or more nonvolatile storage devices accessible by the heterogeneous processors; and a code execution load balancing tool for load balancing code execution, the code execution load balancing tool comprising software code effective to: compile a first source code subtask and a second source code subtask, the compiling resulting in a first byte code subtask and a second byte code subtask; determine whether to store a pointer in a byte code file, the pointer including a stored location that corresponds to the second byte code subtask; store the pointer in the byte code file in response to the determination; store the second byte code subtask at the stored location in response to the determination; translate the first byte code subtask to a first object code subtask; execute the first object code subtask using one of the plurality of heterogeneous processors; during the execution of the first object code subtask, the software code being further effective to: retrieve the pointer and analyze the stored location; in response to analyzing the stored location, retrieve the second byte code subtask using a runtime loader; in response to retrieving the second byte code subtask, use the runtime loader to identify a selected processor type from the plurality of heterogeneous processor types in which to execute the second byte code subtask, wherein the identifying includes software code effective to retrieve a loading factor for each of the plurality of heterogeneous processor types and determine an availability of each of the plurality of heterogeneous processor types using the loading factors; in response to identifying the selected processor type, use the runtime loader to translate the second byte code subtask to a second object code subtask; and load the second object code subtask into a second processor, selected from the plurality of heterogeneous processors, that corresponds to the selected processor type. 2. A computer program product stored on a computer memory, the computer memory containing instructions for execution by a computer, which, when executed by the computer, cause the computer to implement a method for load balancing code execution, said method comprising: compiling a first source code subtask and a second source code subtask, the compiling resulting in a first byte code subtask and a second byte code subtask; determining whether to store a pointer in a byte code file, the pointer including a stored location that corresponds to the second byte code subtask; storing the pointer in the byte code file in response to the determination; storing the second byte code subtask at the stored location in response to the determination; translating the first byte code subtask to a first object code subtask; executing the first object code subtask using one of a plurality of heterogeneous processor types; during the execution of the first object code subtask, the method further comprising: retrieving the pointer and analyzing the stored location; in response to analyzing the stored location, retrieving the second byte code subtask using a runtime loader; in response to retrieving the second byte code subtask, using the runtime loader to identify a processor type from the plurality of heterogeneous processor types in which to execute the second byte code subtask, wherein the identifying includes retrieving a loading factor for each of the plurality of heterogeneous processor types and determining an availability of each of the plurality of heterogeneous processor types using the loading factors; in response to identifying the processor type, using the runtime loader to translate the second byte code subtask to a second object code subtask; and loading the second object code subtask into a processor that corresponds to the identified processor type. 3. A method for load balancing code execution, said method comprising: compiling a first source code subtask and a second source code subtask, the compiling resulting in a first byte code subtask and a second byte code subtask; determining whether to store a pointer in a byte code file, the pointer including a stored location that corresponds to the second byte code subtask; storing the pointer in the byte code file in response to the determination; storing the second byte code subtask at the stored location in response to the determination; translating the first byte code subtask to a first object code subtask; executing the first object code subtask using one of a plurality of heterogeneous processor types; during the execution of the first object code subtask, the method further comprising: retrieving the pointer and analyzing the stored location; in response to analyzing the stored location, retrieving the second byte code subtask using a runtime loader; in response to retrieving the second byte code subtask, using the runtime loader to identify a processor type from the plurality of heterogeneous processor types in which to execute the second byte code subtask, wherein the identifying includes retrieving a loading factor for each of the plurality of heterogeneous processor types and determining an availability of each of the plurality of heterogeneous processor types using the loading factors; in response to identifying the processor type, using the runtime loader to translate the second byte code subtask to a second object code subtask; and loading the second object code subtask into a processor that corresponds to the identified processor type.
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Miller,Matthew; Walker,Robert L., Method and system for managing distribution of computer-executable program threads between central processing units in a multi-central processing unit computer system.
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