IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
|
| 국제특허분류(IPC7판) |
|
| 출원번호 |
UP-0493069
(2006-07-26)
|
| 등록번호 |
US-7709269
(2010-06-03)
|
|
발명자
/ 주소 |
- Smith, Richard Peter
- Sheppard, Scott T.
|
| 출원인 / 주소 |
|
| 대리인 / 주소 |
Myers Bigel Sibley & Sajovec, P.A.
|
| 인용정보 |
피인용 횟수 :
71 인용 특허 :
127 |
초록
▼
Transistors are fabricated by forming a protective layer having a first opening extending therethrough on a substrate, forming a dielectric layer on the protective layer having a second opening extending therethrough that is wider than the first opening, and forming a gate electrode in the first and
Transistors are fabricated by forming a protective layer having a first opening extending therethrough on a substrate, forming a dielectric layer on the protective layer having a second opening extending therethrough that is wider than the first opening, and forming a gate electrode in the first and second openings. A first portion of the gate electrode laterally extends on surface portions of the protective layer outside the first opening, and a second portion of the gate electrode is spaced apart from the protective layer and laterally extends beyond the first portion on portions of the dielectric layer outside the second opening. Related devices and fabrication methods are also discussed.
대표청구항
▼
That which is claimed: 1. A method of fabricating a transistor, the method comprising: forming a protective layer; forming a dielectric layer on the protective layer, the dielectric layer having a recess extending therethrough and exposing a portion of the protective layer, wherein the protective l
That which is claimed: 1. A method of fabricating a transistor, the method comprising: forming a protective layer; forming a dielectric layer on the protective layer, the dielectric layer having a recess extending therethrough and exposing a portion of the protective layer, wherein the protective layer and the dielectric layer comprise different materials; patterning the protective layer using the dielectric layer as a mask to form a first opening extending through the protective layer; then widening the recess in the dielectric layer to define a second opening extending therethrough that is wider than the first opening, the second opening exposing the first opening and exposing surface portions of the protective layer on opposite sides of the first opening; forming a gate material in the first and second openings and on the dielectric layer outside the second opening; and patterning the gate material on the dielectric layer outside the second opening to define a gate electrode including first and second laterally extending portions, wherein the first portion of the gate electrode laterally extends on surface portions of the protective layer outside the first opening and wherein the second portion of the gate electrode laterally extends beyond the first portion on portions of the dielectric layer outside the second opening. 2. The method of claim 1, wherein the dielectric layer has a lower dielectric index than the protective layer. 3. The method of claim 2, wherein the dielectric layer comprises an oxide layer. 4. The method of claim 3, wherein forming the dielectric layer comprises performing a chemical vapor deposition (CVD) process at a temperature of about 900 degrees Celsius (C) to form a high-temperature oxide (HTO) layer on the protective layer. 5. The method of claim 1, wherein the dielectric layer comprises a high-quality oxide layer having a dielectric index of less than about 1.5. 6. The method of claim 1, wherein the dielectric layer has a thickness greater than that of the protective layer. 7. The method of claim 6, wherein the dielectric layer has a thickness of about 500 Angstroms (Å) to about 3000 Å, and wherein the protective layer has a thickness of about 200 Å to about 2000 Å. 8. The method of claim 1, wherein widening the recess in the dielectric layer comprises: symmetrically expanding the recess in the dielectric layer so that the second opening and the first opening are self-aligned. 9. The method of claim 8, wherein symmetrically expanding the recess in the dielectric layer comprises: etching the dielectric layer using a wet oxide etchant, wherein the wet oxide etchant is selective with respect to the protective layer. 10. The method of claim 1, further comprising: forming a channel layer; and forming a barrier layer on the channel layer, wherein forming the protective layer comprises forming the protective layer on the barrier layer, wherein forming the gate electrode comprises forming the gate electrode extending through the first opening in the protective layer to contact the barrier layer, and wherein a junction between the channel layer and the barrier layer define a heterojunction. 11. The method of claim 10, further comprising: forming first and second ohmic contact regions on the barrier layer adjacent to and spaced apart from the protective layer so that the protective layer is between the first and second ohmic contact regions. 12. The method of claim 11, wherein forming the first and second ohmic contact regions comprises: patterning the dielectric layer and the protective layer to expose first and second portions of the barrier layer; and after patterning the dielectric layer and the protective layer, respectively forming the first and second ohmic contact regions on the first and second portions of the barrier layer adjacent to and spaced apart from the patterned protective layer. 13. The method of claim 12, wherein patterning the dielectric layer and the protective layer comprises: before forming the dielectric layer, patterning the protective layer to expose the first and second portions of the barrier layer, wherein forming the dielectric layer comprises forming the dielectric layer on the protective layer and on the first and second portions of the barrier layer; and then patterning the dielectric layer to define first and second recesses therein respectively exposing the first and second portions of the barrier layer. 14. The method of claim 12, wherein patterning the dielectric layer and the protective layer comprises: patterning the dielectric layer to expose first and second portions of the protective layer; and patterning the protective layer using the dielectric layer as a mask to expose the first and second portions of the barrier layer. 15. The method of claim 1, wherein forming the gate electrode further comprises: forming the gate electrode in the first opening directly on opposing sidewalls of the protective layer. 16. The method of claim 1, wherein forming the gate electrode comprises: forming a dielectric liner in the first opening on opposing sidewalls of the protective layer; and after forming the dielectric liner, forming the gate electrode in the first opening directly on the dielectric liner. 17. The method of claim 1, wherein the gate electrode is directly on the barrier layer, wherein the first portion of the gate electrode laterally extends directly on the protective layer, and wherein the second portion of the gate electrode laterally extends directly on the dielectric layer and substantially parallel to the first portion. 18. A method of fabricating a transistor, the method comprising: forming a protective layer, the protective layer having a first opening extending therethrough, wherein forming the protective layer comprises performing a chemical vapor deposition (CVD) process at a temperature of more than about 900 degrees Celsius (C) to form a high-purity nitride (HPN) layer on an underlying layer in a same reactor in which the underlying layer was grown; forming a dielectric layer on the protective layer, the dielectric layer having a second opening extending therethrough that is wider than the first opening, wherein the dielectric layer comprises an oxide layer having a lower dielectric index than the protective layer, and wherein forming the dielectric layer comprises performing a chemical vapor deposition (CVD) process at a temperature of about 900 degrees Celsius (C) to form a high-temperature oxide (HTO) layer on the protective layer; forming a gate material in the first and second openings and on the dielectric layer outside the second opening; and patterning the gate material on the dielectric layer outside the second opening to define a gate electrode including first and second laterally extending portions, wherein the first portion of the gate electrode laterally extends on surface portions of the protective layer outside the first opening and wherein the second portion of the gate electrode laterally extends beyond the first portion on portions of the dielectric layer outside the second opening. 19. The method of claim 18, wherein the protective layer comprises stoichiometric silicon nitride, and wherein the dielectric layer comprises silicon dioxide. 20. A method of fabricating a transistor, the method comprising: forming a protective layer; forming a dielectric layer on the protective layer, the dielectric layer having a recess extending therethrough and exposing a portion of the protective layer; patterning the protective layer using the dielectric layer as a mask to form a first opening extending through the protective layer; then widening the recess in the dielectric layer to define a second opening in the dielectric layer that is wider than the first opening and exposing surface portions of the protective layer on opposite sides of the first opening; and forming a gate electrode in the first and second openings so that a first portion of the gate electrode laterally extends on surface portions of the protective layer outside the first opening and so that a second portion of the gate electrode laterally extends beyond the first portion on portions of the dielectric layer outside the second opening. 21. A method of fabricating a transistor, the method comprising: providing a protective layer; providing a dielectric layer on the protective layer, the dielectric layer having a recess extending therethrough and exposing a portion of the protective layer; patterning the protective layer using the dielectric layer as a mask; then widening the recess in the dielectric layer; and providing a gate electrode on the protective layer and on the dielectric layer, the gate electrode comprising a first portion that laterally extends on surface portions of the protective layer and a second portion that laterally extends on surface portions of the dielectric layer outside the widened recess and beyond the first portion. 22. The method of claim 21, wherein patterning the protective layer comprises: patterning the protective layer using the dielectric layer as a mask to form a first opening extending through the protective layer. 23. The method of claim 22, wherein widening the recess in the dielectric layer comprises: widening the recess in the dielectric layer to define a second opening in the dielectric layer that is wider than the first opening in the protective layer and exposes the surface portions of the protective layer on opposite sides of the first opening. 24. The method of claim 23, wherein widening the recess in the dielectric layer comprises: symmetrically expanding the recess in the dielectric layer so that the second opening and the first opening are self-aligned.
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