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RF circuits including transistors having strained material layers 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-031/00
출원번호 UP-0032413 (2005-01-10)
등록번호 US-7709828 (2010-06-03)
발명자 / 주소
  • Braithwaite, Glyn
  • Hammond, Richard
  • Currie, Matthew
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, Ltd.
대리인 / 주소
    Slater & Matsil, L.L.P.
인용정보 피인용 횟수 : 126  인용 특허 : 158

초록 ▼

Circuits for processing radio frequency (“RF”) and microwave signals are fabricated using field effect transistors (“FETs”) that have one or more strained channel layers disposed on one or more planarized substrate layers. FETs having such a configuration exhibit improved

대표청구항 ▼

What is claimed is: 1. A circuit for processing an RF signal comprising at least one FET to which the RF signal is applied, the at least one FET comprising: a semiconductor substrate including at least one planarized layer; a channel region including at least one strained channel layer disposed on

이 특허에 인용된 특허 (158)

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  145. Ek Bruce A. (Pelham Manor NY) Iyer Subramanian S. (Yorktown Heights NY) Pitner Philip M. (Wappingers Falls NY) Powell Adrian R. (New Milford CT) Tejwani Manu J. (Yorktown Heights NY), Substrate for tensilely strained semiconductor.
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  146. Roberds, Brian; Doyle, Brian S., Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel.
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  148. Bertin Claude L. (South Burlington VT) DiMaria Donelli J. (Ossining NY) Miyakawa Makoto (Tokyo JPX) Sakaue Yoshinori (Tokyo JPX), Three-dimensional direct-write EEPROM arrays and fabrication methods.
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  86. Thompson, Scott E.; Shifren, Lucian; Ranade, Pushkar; Scudder, Lance; Zhao, Dalong; Bakhisher, Teymur; Pradhan, Sameer, Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom.
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  89. Scudder, Lance S.; Ranade, Pushkar; Stager, Charles; Sridharan, Urupattur C.; Zhao, Dalong, Reducing or eliminating pre-amorphization in transistor manufacture.
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  90. Scudder, Lance; Ranade, Pushkar; Stager, Charles; Sridharan, Urupattur C.; Zhao, Dalong, Reducing or eliminating pre-amorphization in transistor manufacture.
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  106. Wang, Lingquan; Bakhishev, Teymur; Zhao, Dalong; Ranade, Pushkar; Pradhan, Sameer; Hoffmann, Thomas; Shifren, Lucian; Scudder, Lance, Semiconductor structure with reduced junction leakage and method of fabrication thereof.
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  108. Scudder, Lance; Ranade, Pushkar; Stager, Charles; Shifren, Lucian; Zhao, Dalong; Sridharan, U.C.; Duane, Michael, Semiconductor structure with substitutional boron and method for fabrication thereof.
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  124. Arghavani, Reza; Ranade, Pushkar; Shifren, Lucian; Thompson, Scott E.; de Villeneuve, Catherine, Transistor with threshold voltage set notch and method of fabrication thereof.
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  125. Arghavani, Reza; Ranade, Pushkar; Shifren, Lucian; Thompson, Scott E.; de Villeneuve, Catherine, Transistor with threshold voltage set notch and method of fabrication thereof.
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AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

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