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An embodiment of a flash memory device with NAND architecture, including a matrix of data storage memory cells each one having a programmable threshold voltage, wherein the matrix is arranged in a plurality of rows and columns with the memory cells of each row being connected to a corresponding word

An embodiment of a flash memory device with NAND architecture, including a matrix of data storage memory cells each one having a programmable threshold voltage, wherein the matrix is arranged in a plurality of rows and columns with the memory cells of each row being connected to a corresponding word line and the memory cells of each column being arranged in a plurality of strings of memory cells, the memory cells in each string being connected in series, the strings of each column being coupled to a reference voltage distribution line distributing a reference voltage by means of a first selector, wherein each string further includes at least one first shielding element interposed between the memory cells of the string and said first selector, the first shielding element being adapted to shield the memory cells from electric fields that, in operation, arise between the string of memory cells and the first selector.

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The invention claimed is: 1. A flash memory device with NAND architecture, the flash memory device comprising: a matrix of data storage memory cells each data storage memory cell having a programmable threshold voltage, the matrix comprising: a plurality of rows and columns with the memory cells of

The invention claimed is: 1. A flash memory device with NAND architecture, the flash memory device comprising: a matrix of data storage memory cells each data storage memory cell having a programmable threshold voltage, the matrix comprising: a plurality of rows and columns with the memory cells of each row being connected to a corresponding word line and the memory cells of each column being arranged in a plurality of strings of memory cells, the memory cells in each string being connected in series, the strings of each column being coupled to a reference voltage distribution line distributing a reference voltage by a first selector, wherein each string further includes at least one first shielding element interposed between the memory cells of the string and said first selector, the first shielding element receiving a shielding voltage and configured to shield the memory cells from electric fields that, during reading and program operations, arise between the string of memory cells and the first selector; and wherein: the reference voltage having a magnitude that is less than the magnitude of the shielding voltage. 2. The memory device according to claim 1, wherein the strings of each column are coupled to a corresponding bit line by a second selector, each string including at least one second shielding element interposed between the memory cells of the string and said second selector, said second shielding element configured to shield the memory cells from electric fields that, during reading and program operations, arise between the string of memory cells and the second selector. 3. The memory device according to claim 2, wherein the at least one first shielding element includes at least one dummy memory cell structurally similar to the data storage memory cells. 4. The memory device according to claim 3, wherein the at least one second shielding element includes at least one dummy memory cell structurally similar to the data storage memory cells. 5. The memory device according to claim 4, wherein the matrix of memory cells includes at least one individually erasable sector, and wherein the memory cells, the first shielding element and the second shielding element belonging to each string of the at least one sector have a corresponding bulk terminal, the memory device further including means for erasing the at least one sector, said means for erasing being adapted to apply the reference voltage to the dummy cells of the first and second shielding elements, and to the word lines connected to the memory cells of the at least one sector, and to apply an erasing voltage to the bulk terminal of the memory cells, and to the bulk terminal of the dummy cells of the first and second shielding elements. 6. A method of accessing data storage memory cells of a flash memory device with NAND architecture, wherein the memory device includes a matrix of memory cells each one having a programmable threshold voltage, the matrix being arranged in a plurality of rows and columns with the memory cells of each row being connected to a corresponding word line and the memory cells of each column being arranged in a plurality of strings of memory cells with the memory cells of each string being connected in series, the strings of each column being coupled to a reference voltage distribution line distributing a reference voltage by a first selector, the method including: providing for each string at least one first shielding element receiving a shielding voltage and interposed between the memory cells of the string and said first selector; and using the first shielding element as a shield for shielding the memory cells of the respective string from electric fields that, during reading and program operations, arise between the string of memory cells and the first selector; and wherein: the reference voltage having a magnitude that is less than the magnitude of the shielding voltage. 7. The method according to claim 6, wherein the strings of each column being connected to a corresponding bit line by a second selector, further includes the steps of: providing at least one second shielding element interposed between the memory cells of the string and said second selector; and using the second shielding element as a shield for shielding the memory cells of the respective string from electric fields that, during reading and program operations, arise between the string of memory cells and the second selector. 8. The method according to claim 6, wherein either one or both of said first and second shielding elements include each at least one respective dummy memory cell structurally identical to the data storage memory cells. 9. The method according to claim 8, wherein the matrix of memory cells includes at least one sector individually erasable, and the memory cells, the first shielding element and the second shielding element have a corresponding bulk terminal, the method including: selecting at least one sector; applying the reference voltage to the dummy-cells of the first and second shielding elements, and to the word lines connected to the memory cells of the at least one sector; and applying an erasing voltage to the bulk terminal of the memory cells, and to the bulk terminal of the dummy cells of the first and second shielding elements. 10. An integrated circuit, comprising: a data node; a reference node; a first nonvolatile memory cell coupled between the data node and the reference node; a data selector coupled between the first nonvolatile memory cell and the data node; a reference selector coupled between the first nonvolatile memory cell and the reference node; and a first shielding device coupled between the first nonvolatile memory cell and one of the data selector and the reference selector, the first shielding device receiving a shielding voltage and configured to shield the first nonvolatile memory cell from electric fields that, during reading and program operations, arise between the first nonvolatile memory cell and one of the data selector and the reference selector; and wherein: the reference voltage having a magnitude that is less than the magnitude of the shielding voltage. 11. The integrated circuit of claim 10, further comprising: a bit line coupled to the data node; and a source line coupled to the reference node. 12. The integrated circuit of claim 10, further comprising a second nonvolatile memory cell serially coupled between the first nonvolatile memory cell and one of the data and reference the data selector and the reference selector. 13. The integrated circuit of claim 10 wherein: the data selector comprises a first transistor; and the reference selector comprises a second transistor. 14. The integrated circuit of claim 10 wherein the shielding device comprises a second nonvolatile memory device from which data is not read. 15. The integrated circuit of claim 10, further comprising a second shielding device coupled between the first nonvolatile memory cell and the other of the data selector and the reference selector, the second shielding device configured to shield the first nonvolatile memory cell from electric fields that, during reading and program operations, arise between the first nonvolatile memory cell and the other of the data selector and the reference selectors. 16. A system, comprising: a first integrated circuit including: a data node; a reference node; a first nonvolatile memory cell coupled between the data node and the reference node; a data selector coupled between the first nonvolatile memory cell and the data node; a reference selector coupled between the first nonvolatile memory cell and the reference node; and a first shielding device coupled between the first nonvolatile memory cell and one of the data selector and the reference selector, the first shielding device receiving a shielding voltage and configured to shield the first nonvolatile memory cell from electric fields that, during reading and program operations, arise between the first nonvolatile memory cell and one of the data selector and the reference selector; and a second integrated circuit coupled to the first integrated circuit; and wherein: the reference voltage having a magnitude that is less than the magnitude of the shielding voltage. 17. The system of claim 16 wherein the second integrated circuit comprises a controller. 18. A method, comprising: generating a programming voltage on a control node of a first nonvolatile memory cell; generating a shielding voltage on a control node of a shielding transistor that is serially coupled to the first nonvolatile memory cell, the shielding voltage having a magnitude that is less than a magnitude of the programming voltage, wherein the shielding transistor is configured to shield the first nonvolatile memory cell from electric fields that, during reading and program operations, arise between the first nonvolatile memory cell and one of the control node and a reference node; and generating a non-programming voltage on a control node of a second nonvolatile memory cell that is serially coupled between the first memory cell and the shielding transistor, the non-programming voltage having a magnitude that is between the magnitudes of the programming and shielding voltages. 19. The method of claim 18, further comprising: isolating the shielding transistor from the reference node with an inactive transistor; and generating on the reference node a reference voltage having a magnitude that is less than the magnitude of the shielding voltage. 20. The method of claim 18, further comprising: coupling the shielding transistor to a data line with an active transistor; and generating on the data line a data voltage having a magnitude that is less than the magnitude of the shielding voltage.