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특허 상세정보

Tri-gate transistor device with stress incorporation layer and method of fabrication

특허상세정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) H01L-029/06   
미국특허분류(USC) 257/401; 257/623; 257/E29.022
출원번호 UP-0493789 (2006-07-25)
등록번호 US-7714397 (2010-06-03)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman LLP
인용정보 피인용 횟수 : 13  인용 특허 : 174
초록

A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body w...

대표
청구항

We claim: 1. A semiconductor device comprising: a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate; a gate dielectric formed on said laterally opposite sidewalls of said semiconductor body; a gate electrode formed over said top surface of said semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body; and a film formed beneath said semiconductor body wherein said film produces a stress in said semiconductor body. 2. The device of claim 1, furth...

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