Method and system for allowing code to be securely initialized in a computer
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-012/14
G06F-021/22
출원번호
UP-0152909
(2005-06-15)
등록번호
US-7721341
(2010-06-10)
발명자
/ 주소
England, Paul
Willman, Bryan
출원인 / 주소
Microsoft Corporation
인용정보
피인용 횟수 :
9인용 특허 :
108
초록▼
A memory controller prevents CPUs and other I/O bus masters from accessing memory during a code (for example, trusted core) initialization process. The memory controller resets CPUs in the computer and allows a CPU to begin accessing memory at a particular location (identified to the CPU by the memo
A memory controller prevents CPUs and other I/O bus masters from accessing memory during a code (for example, trusted core) initialization process. The memory controller resets CPUs in the computer and allows a CPU to begin accessing memory at a particular location (identified to the CPU by the memory controller). Once an initialization process has been executed by that CPU, the code is operational and any other CPUs are allowed to access memory (after being reset), as are any other bus masters (subject to any controls imposed by the initiated code).
대표청구항▼
The invention claimed is: 1. One or more computer storage media having stored thereon a plurality of instructions that, when executed by one or more processors of a computer, causes the one or more processors to perform acts including: allowing operation of the computer to begin based on untrusted
The invention claimed is: 1. One or more computer storage media having stored thereon a plurality of instructions that, when executed by one or more processors of a computer, causes the one or more processors to perform acts including: allowing operation of the computer to begin based on untrusted code; loading, under control of the untrusted code, a trusted core into memory; preventing each of one or more central processing units and each of one or more bus masters in the computer from accessing the memory; resetting each of the one or more central processing units; after resetting, allowing one central processing unit to access the memory and execute trusted core code beginning at a first instruction, wherein the first instruction is for execution of the trusted core at a beginning of the trusted core; and after allowing the one central processing unit to access the memory, allowing any other central processing units and any bus masters in the computer to access the memory and execute the trusted core code beginning at a different instruction than the first instruction, wherein the different instruction is for execution of the trusted core at a location independent of the beginning of the trusted core. 2. One or more computer storage media as recited in claim 1, wherein the one or more processors comprise one or more controllers of one or more memory controllers. 3. One or more computer storage media as recited in claim 1, wherein the preventing comprises preventing each of the one or more central processing units and each of the one or more bus masters from accessing the memory in response to an initialize trusted core command received from one of the one or more central processing units. 4. One or more computer storage media as recited in claim 1, wherein the loading the trusted core comprises copying different parts of the trusted core from one or more sources and combining the different parts to assemble the trusted core. 5. One or more computer storage media as recited in claim 4, wherein combining the different parts comprises exclusive-ORing bits of the different parts. 6. One or more computer storage media as recited in claim 1, wherein the plurality of instructions further cause the one or more processors to perform acts including: extracting a cryptographic measure of the trusted core in the memory; and storing the extracted cryptographic measure. 7. One or more computer storage media as recited in claim 6, wherein the plurality of instructions further cause the one or more processors to perform acts including: resetting a cryptographic processor; requesting the cryptographic processor to extract the cryptographic measure; and receiving the extracted cryptographic measure from the cryptographic processor. 8. One or more computer storage media as recited in claim 1, wherein the resetting comprises asserting, on a processor bus, a RESET#signal to each of the one or more central processing units. 9. One or more computer storage media as recited in claim 1, wherein the resetting comprises clearing a state of each of the one or more central processing units. 10. A method comprising: allowing a computer to begin operation based on untrustworthy code; loading, under the control of the untrustworthy code, additional code into memory; and initiating execution of the additional code in a secure manner despite the untrustworthy code in the computer, the initiating including: receiving a read request corresponding to a central processing unit reset vector from a first central processing unit of the computer; using an association between the central processing unit reset vector and an initialization vector for the additional code to return, in response to the read request, the initialization vector rather than the processor reset vector; and allowing access to the memory beginning with the initialization vector. 11. A method as recited in claim 10, wherein the initiating further comprises initiating execution of the additional code in a secure manner despite both the untrustworthy code in the computer and other pre-existent state of the computer. 12. A method as recited in claim 10, wherein the initiating execution of the additional code in a secure manner comprises: preventing each of one or more central processing units in the computer from accessing the memory; preventing each of one or more bus masters in the computer from accessing the memory; resetting each of the one or more central processing units; allowing the first central processing unit to access the memory and execute a code initialization process; and after execution of the code initialization process, allowing any other central processing units and any of the one or more bus masters to access the memory. 13. A method as recited in claim 10, wherein the initiating comprises initiating execution of the additional code in a secure manner without requiring any additional bus transactions to be supported by the first central processing unit. 14. A method as recited in claim 10, further comprising: remapping the additional code to appear at an address where the first central processing unit starts executing after being reset. 15. A method as recited in claim 10, further comprising: receiving, from a second central processing unit of the computer, a second read request corresponding to the central processing unit reset vector; responding to the second read request with instructions to cause the central processing unit to begin executing the additional code at a different instruction than the first central processing unit began executing the additional code. 16. A method as recited in claim 10, wherein the loading the additional code comprises copying different portions of the additional code from a plurality of different sources including one or more of: a local mass storage device, a remote device, and a local chipset. 17. A memory controller comprising: a first interface to allow communication with a processor; a second interface to allow communication with a system memory; and a controller, coupled to the first interface and the second interface, to reset the processor, to allow the processor to execute a code initialization process beginning at a first instruction while preventing any other processors coupled to the memory controller from accessing the system memory, and to subsequently allow any of the other processors to access the system memory beginning at a second instruction that is different than the first instruction, wherein the first instruction is for execution of a trusted core at a beginning of the trusted core and the second instruction is for execution of the trusted core at a location independent of the beginning of the trusted core. 18. A memory controller as recited in claim 17, wherein the controller is further to allow the processor to execute the code initialization process while preventing any bus masters from accessing the system memory. 19. A memory controller as recited in claim 17, wherein the controller is further to: reset any other processor coupled to the memory controller prior to allowing the processor to execute the code initialization process; prevent any other processor and any bus master coupled to the memory controller from accessing the system memory until the one process executes the code initialization process; and after execution of the code initialization process, allow any other central processing units coupled to the memory controller and any bus masters coupled to the memory controller to access the system memory beginning at the second instruction. 20. A memory controller as recited in claim 17, wherein the controller is to reset the processor by asserting, on a processor bus, a reset signal to the processor, wherein the reset signal comprises RESET#.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (108)
Campbell Randall B., Apparatus and method for remotely executing commands using distributed computing environment remote procedure calls.
Fisher Jerald C. ; Nguyen Lien Dai ; Young James ; Seaburg Gunnar P. ; Hedlund Galen W. ; Katz Richard S., Channel configuration program server architecture.
Takahashi Kikuo (Hachioji JPX) Kagimasa Toyohiko (Hachioji JPX) Mori Toshiaki (Hachioji JPX), Data processing apparatus having a real memory region with a corresponding fixed memory protection key value and method.
Robert G. Atkinson ; James W. Kelly, Jr. ; Bryan W. Tuttle ; Robert M. Price ; Robert P. Reichel, Embedding certifications in executable files for network transmission.
Bizzaro Mario,ITX ; Condorelli Vincenzo ; Hack Michel Henri Theodore ; Kravitz Jeffrey Kenneth ; Lindemann Mark John ; Palmer Elaine Rivette ; Pedrina Gianluca,ITX ; Smith Sean William ; Weingart Ste, Hardware access control locking.
Benantar Messaoud ; Blakley ; III George Robert ; Nadalin Anthony Joseph, Information handling system, method, and article of manufacture for efficient object security processing by grouping obj.
Guillou Louis C. (Rennes FRX) Quisquater Jean-Jacques (Brussels BEX), Method and apparatus for authenticating accreditations and for authenticating and signing messages.
Stumpf Bernard (Chelmsford MA) Stabler George M. (Nashua NH) Bahr Richard G. (Cambridge MA) Ciavaglia Stephen J. (Nashua NH) Flahive Barry J. (Westford MA) Lauer Hugh (Concord MA), Method and apparatus for bus lock during atomic computer operations.
Novoa Manuel ; McCann Paul H. ; Sharum Wayne P. ; Crisan Adrian ; Hokanson Paul B., Method and apparatus for remote ROM flashing and security management for a computer system.
Hennige Hartmut (23 Packman Lane ; Home Green Kirk Ella Hull HU10 7TH N. Humberside GB3), Method and device for simplifying the use of a plurality of credit cards, or the like.
Chan, Shannon; Jensenworth, Gregory; Goertzel, Mario C.; Shah, Bharat; Swift, Michael M.; Ward, Richard B., Method and system for secure running of untrusted content.
Krishnan Ganapathy ; Guthrie John ; Oyler Scott, Method and system for securely incorporating electronic information into an online purchasing application.
Boyle John ; Holden James M. ; Levin Stephen E. ; Maiwald Eric S. ; Nickel James O. ; Snow David Wayne ; Wrench ; Jr. Edwin H., Method for establishing trust in a computer network via association.
Graunke Gary L. ; Carbajal John ; Maliszewski Richard L. ; Rozas Carlos V., Method for securely distributing a conditional use private key to a trusted entity on a remote system.
DeRoo David T. ; Nicol Mark D. ; DeLisle David J. ; Krau Michael P. ; Fakhruddin Saifuddin ; Gauthier Lloyd W. ; Kohtz Robert A., Method to store privileged data within the primary CPU memory space.
Johnson Herrick J. (Marblehead MA) Olson Margaret (Nashua NH) Jones Stuart (Cambridge MA) Bodoff Stephanie (Somerville MA) Bertrand Stephen C. (Waltham MA) Levine Paul H. (Carlisle MA), Network license server.
Rabne Michael W. ; Barker James A. ; Alrashid Tareq M.T. ; Christian Brian S. ; Cox Steven C. ; Slotta Elizabeth A. ; Upthegrove Luella R., Rights management system for digital media.
McMullan ; Jr. Jay C. (Doraville GA) Burleson David B. (Roswell GA) Borsetti ; Jr. Paul (Alpharetta GA) Filion John T. (Lawrenceville GA), Secure authorization and control method and apparatus for a game delivery service.
Grimonprez Georges (Villeneuve d\Asq FRX) Paradinas Pierre (Villeneuve d\Asq FRX), Secured method for loading a plurality of applications into a microprocessor memory card.
Mandelbaum Richard (Manalapan NJ) Sherman Stephen A. (Hackettstown NJ) Wetherington Diane R. (Bernardsville NJ), Smartcard adapted for a plurality of service providers and for remote installation of same.
Van Wie David M. ; Weber Robert P., Steganographic techniques for securely delivering electronic digital rights management control information over insecure.
David M. Van Wie ; Robert P. Weber, Steganographic techniques for securely delivering electronic digital rights management control information over insecure communication channels.
Van Wie David M. ; Weber Robert P., Steganographic techniques for securely delivering electronic digital rights management control information over insecure communication channels.
Barlow Doug ; Dillaway Blair ; Fox Barbara ; Lipscomb Terry ; Spies Terrence, System and method for configuring and managing resources on a multi-purpose integrated circuit card using a personal computer.
Ryan ; Jr. Frederick W. ; Sisson Robert W., System and method for mutual authentication and secure communications between a postage security device and a meter server.
Ginter Karl L. ; Shear Victor H. ; Spahn Francis J. ; Van Wie David M., System and methods for secure transaction management and electronic rights protection.
Shear Victor H. ; Van Wie David M. ; Weber Robert P., Systems and methods for matching, selecting, narrowcasting, and/or classifying based on rights management and/or other information.
Ginter Karl L. ; Shear Victor H. ; Sibert W. Olin ; Spahn Francis J. ; Van Wie David M., Systems and methods for secure transaction management and electronic rights protection.
Ginter Karl L. ; Shear Victor H. ; Spahn Francis J. ; Van Wie David M., Systems and methods for secure transaction management and electronic rights protection.
Ginter Karl L. ; Shear Victor H. ; Spahn Francis J. ; Van Wie David M., Systems and methods for secure transaction management and electronic rights protection.
Ginter Karl L. ; Shear Victor H. ; Spahn Francis J. ; Van Wie David M., Systems and methods for secure transaction management and electronic rights protection.
Ginter Karl L. ; Shear Victor H. ; Spahn Francis J. ; Van Wie David M., Systems and methods for secure transaction management and electronic rights protection.
Ginter Karl L. ; Shear Victor H. ; Spahn Francis J. ; Van Wie David M., Systems and methods for secure transaction management and electronic rights protection.
Karl L. Ginter ; Victor H. Shear ; Francis J. Spahn ; David M. Van Wie, Systems and methods for secure transaction management and electronic rights protection.
Karl L. Ginter ; Victor H. Shear ; Francis J. Spahn ; David M. Van Wie, Systems and methods for secure transaction management and electronic rights protection.
Karl L. Ginter ; Victor H. Shear ; Francis J. Spahn ; David M. Van Wie, Systems and methods for secure transaction management and electronic rights protection.
Ginter Karl L. ; Shear Victor H. ; Spahn Francis J. ; Van Wie David M., Systems and methods for the secure transaction management and electronic rights protection.
Hall Edwin J. ; Shear Victor H. ; Tomasello Luke S. ; Van Wie David M. ; Weber Robert P. ; Worsencroft Kim ; Xu Xuejun, Techniques for defining using and manipulating rights management data structures.
Hall Edwin J. ; Shear Victor H. ; Tomasello Luke S. ; Van Wie David M. ; Weber Robert P. ; Worsencroft Kim ; Xu Xuejun, Techniques for defining, using and manipulating rights management data structures.
Ginter Karl L. ; Shear Victor H. ; Spahn Francis J. ; Van Wie David M. ; Weber Robert P., Trusted and secure techniques, systems and methods for item delivery and execution.
Boyle John ; Holden James M. ; Levin Stephen E. ; Maiwald Eric S. ; Nickel James O. ; Snow ; deceased David Wayne ; Wrench ; Jr. Edwin H., Using trusted associations to establish trust in a computer network.
Novak, Mark F.; Spiger, Robert Karl; Thom, Stefan; Linsley, David J.; Field, Scott A.; Thomas, Anil Francis, Device booting with an initial protection component.
Novak, Mark F.; Spiger, Robert Karl; Thom, Stefan; Linsley, David J.; Field, Scott A.; Thomas, Anil Francis, Device booting with an initial protection component.
Ayyar, Mani; Delano, Eric Richard; Schoinas, Ioannis Y.; Kumar, Akhilesh; Jayasimha, Doddaballapur; Vargas, Jose A., Method, system, and apparatus for dynamic reconfiguration of resources.
Ayyar, Mani; Delano, Eric Richard; Schoinas, Ioannis Y.; Kumar, Akhilesh; Jayasimha, Doddaballapur; Vargas, Jose A., Method, system, and apparatus for dynamic reconfiguration of resources.
Ayyar, Mani; Delano, Eric; Schoinas, Ioannis T.; Kumar, Akhilesh; Jayasimha, Jay; Vargas, Jose A., Method, system, and apparatus for dynamic reconfiguration of resources.
Ayyar, Mani; Delano, Eric; Schoinas, Ioannis T.; Kumar, Akhilesh; Jayasimha, Jay; Vargas, Jose A., Method, system, and apparatus for dynamic reconfiguration of resources.
Ayyar, Mani; Chennupaty, Srinivas; Kumar, Akhilesh; Jayasimha, Doddabaliapur Narasimha-Murthy; Nachimuthu, Murugasamy; Mannava, Phanindra K.; Schoinas, Ioannis T., Method, system, and apparatus for system level initialization by conveying capabilities and identifiers of components.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.