초록 ▼

A DLL circuit includes a delay line for delaying a clock signal, the delay line including a plurality of cascade-connected variable delay elements, the variable delay elements having a differential circuit structure in which a delay value thereof can be varied by a bias current, a first controller f

A DLL circuit includes a delay line for delaying a clock signal, the delay line including a plurality of cascade-connected variable delay elements, the variable delay elements having a differential circuit structure in which a delay value thereof can be varied by a bias current, a first controller for setting the bias current, and a second controller for selecting an output-producing variable delay element from the plural its of the variable delay elements.

대표청구항 ▼

What is claimed is: 1. A DLL circuit comprising: a delay line for delaying a clock signal, the delay line including a plurality of cascade-connected variable delay elements, the variable delay elements having a differential circuit structure in which a delay value thereof can be varied by a bias cu

What is claimed is: 1. A DLL circuit comprising: a delay line for delaying a clock signal, the delay line including a plurality of cascade-connected variable delay elements, the variable delay elements having a differential circuit structure in which a delay value thereof can be varied by a bias current, the variable delay elements comprising a plurality of bias transistors and a switching circuit connected to a gate of the plurality of bias transistors; a first controller for setting the bias current by controlling the switching circuit to select a bias transistor of the plurality of bias transistors; and a second controller for selecting an output-producing variable delay element from the plurality of the variable delay elements, the second controller including: a phase comparator for comparing a phase of the clock signal and an internal clock signal delayed by the delay line; and a counter circuit for performing addition or subtraction based on a results of a phase comparison by the phase comparator, and an other delay line which receives an output of the delay line, the other delay line having a pitch for adjusting the delay value which is less that a pitch for adjusting a delay value of the delay line, wherein the second controller further comprises a bias circuit for controlling the other delay line based on the count value from the counter circuit. 2. The DLL circuit as claimed in claim 1, wherein the variable delay elements include first and second input transistors comprising sources which are connected to a common node, and a variable bias circuit connected between the common node and a first power line; and the clock signal is supplied in differential format to a gate of the first and second input transistor, and the clock signal is output in differential format from drains of the first and second input transistors. 3. The DLL circuit as claimed in claim 2, wherein the variable bias circuit includes the plurality of bias transistors connected in parallel, and the switching circuit for selecting the bias transistors to be activated. 4. The DLL circuit as claimed in claim 3, wherein the switching circuit comprises a switch which is connected to the gate of a bias transistor of the plurality of bias transistors. 5. The DLL circuit as claimed in claim 3, wherein the first controller varies a first bias voltage supplied to gates of the bias transistors. 6. The DLL circuit as claimed in claim 2, wherein the variable delay elements further have load circuits connected between the drains of the first and second input transistor and a second power line; and the load circuits include first and second load transistors connected in parallel, the first load transistor has a diode connection, and a second bias voltage is supplied to a gate of the second load transistor. 7. The DLL circuit as claimed in claim 6, wherein the second bias voltage follows a variations of a power voltage supplied to the second power line. 8. The DLL circuit as claimed in claim 1, wherein the plurality of bias transistors have mutually differing channel widths and are connected in parallel. 9. A DLL circuit comprising: a delay line for delaying a clock signal, the delay line including a plurality of cascade-connected variable delay elements, the variable delay elements having a differential circuit structure in which a delay value thereof can be varied by a bias current, the variable delay elements comprising a plurality of bias transistors and a switching circuit connected to a gate of the plurality of bias transistors; a first controller for setting the bias current by controlling the switching circuit to select a bias transistor of the plurality of bias transistors; and a second controller for selecting an output-producing variable delay element from the plurality of the variable delay elements, wherein the gate of the plurality of bias transistors comprises a plurality of gates and the switching circuit comprises a plurality of switches connected to the plurality of gates, respectively, and the first controller generates a bias voltage which is supplied to the plurality of gate electrodes via the plurality of switches, wherein the first controller generates a digital bias selection signal for controlling the switching circuit, and varies the delay value of the plurality of variable delay elements by varying at least one of the bias voltage and the bias selection signal, and wherein the first controller comprises: a ring oscillator for generating a reference clock; a clock frequency counter which counts the external clock signals based on the reference clock to detect a frequency of the external clock; and a delay setting circuit for setting delay characteristics of the delay line based on the frequency of the external clock. 10. The DLL circuit as claimed in claim 9, wherein the delay setting circuit comprises a bias generator for generating the bias voltage based on a reference voltage. 11. A semiconductor device comprising: a delay line supplied with a clock signal at an input node and producing a delayed clock signal at an output node, the delay line including a plurality of variable delay elements electrically coupled in series, each of the variable delay elements providing a variable delay value that is controlled by a bias current flowing therethrough, at least one of the variable delay elements electrically connected between the input and output nodes; a reference clock generator generating a reference clock signal independently of each of the clock signal and the delayed clock signal; and a first controller responding to the clock signal and the reference clock signal to control the bias current flowing through each of the variable delay elements. 12. The semiconductor device as claimed in claim 11, wherein the reference clock generator comprises a ring oscillator. 13. The semiconductor device as claimed in claim 12, wherein the first controller comprises a clock frequency counter that counts clock pulses of the clock signal based on the reference clock signal to detect a frequency of the clock signal and a delay setting circuit that sets the bias current of the variable delay elements based on the frequency of the clock signal. 14. The semiconductor device as claimed in claim 11, further comprising a second controller which responds to the clock signal and a replica clock signal relative to the delayed clock signal to determine a number of the variable delay elements to be electrically connected in series between the input and output nodes.