Semiconductor power device with bias circuit
IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
UP-0015890
(2008-01-17)
|
등록번호 |
US-7728671
(2010-06-22)
|
발명자
/ 주소 |
- Blair, Cynthia
- Perugupalli, Prasanth
|
출원인 / 주소 |
|
대리인 / 주소 |
Coats & Bennett, P.L.L.C.
|
인용정보 |
피인용 횟수 :
2 인용 특허 :
2 |
초록
▼
An RF power circuit comprises a power transistor having a gate and drain, an output matching network coupled to the drain and an input matching network coupled to the gate. A closed-loop bias circuit is integrated with the power transistor on the same die and coupled to the gate for biasing the RF p
An RF power circuit comprises a power transistor having a gate and drain, an output matching network coupled to the drain and an input matching network coupled to the gate. A closed-loop bias circuit is integrated with the power transistor on the same die and coupled to the gate for biasing the RF power transistor based on a reference voltage applied to the bias circuit.
대표청구항
▼
What is claimed is: 1. An RF power circuit, comprising: a power transistor having a gate and drain; an output matching network coupled to the drain; an input matching network coupled to the gate; and a closed-loop bias circuit integrated with the power transistor on the same die and coupled to the
What is claimed is: 1. An RF power circuit, comprising: a power transistor having a gate and drain; an output matching network coupled to the drain; an input matching network coupled to the gate; and a closed-loop bias circuit integrated with the power transistor on the same die and coupled to the gate for biasing the power transistor based on a reference voltage applied to the closed-loop bias circuit, the closed-loop bias circuit including a sense circuit operable to sense an output current of the power transistor and an output circuit operable to bias the gate of the power transistor based on a difference between an output of the sense circuit and the reference voltage. 2. The RF power circuit according to claim 1, wherein the reference voltage is externally applied to the closed-loop bias circuit via an external terminal coupled to the closed-loop bias circuit. 3. The RF power circuit according to claim 1, wherein the sense circuit comprises: a resistor coupled between the drain and a further drain of a further transistor; a first operational amplifier having an input coupled to the resistor; and wherein the output circuit has an input coupled to an output of the operational amplifier and an output coupled to the gate of the power transistor. 4. The RF power circuit according to claim 3, wherein the output circuit comprises a second operational amplifier having a first input coupled to the output of the first operational amplifier and a second input that receives the reference voltage. 5. The RF power circuit according to claim 4, wherein an output of the second operational amplifier is coupled to a node of the input matching network. 6. The RF power circuit according to claim 1, wherein the sense circuit includes a start-up circuit operable to cause an output signal of the closed-loop bias circuit to ramp up when activating the RF power circuit. 7. The RF power circuit according to claim 6, wherein the start-up circuit comprises: a transistor; a capacitor charged via a resistor; and wherein a load path of the start-up circuit transistor is coupled in parallel to the capacitor. 8. The RF power circuit according to claim 1, wherein the input matching network includes a capacitor arranged between an external transmission line and the gate, the closed-loop bias circuit is coupled to a node of the input matching network arranged between the transmission line and the capacitor, and the reference voltage is applied to the closed-loop bias circuit via the external transmission line. 9. The RF power circuit according to claim 8, wherein the capacitor is arranged between two shunt capacitors of the input matching network. 10. The RF power circuit according to claim 1, wherein the power transistor comprises a vertical MOS transistor. 11. The RF power circuit according to claim 1, further comprising a regulator coupled to the drain for generating a supply voltage for components of the closed-loop bias circuit. 12. An RF power device assembly, comprising: a substrate; a first terminal; a second terminal; a die including a power transistor having a gate and drain, the die being arranged between the first and second terminals on the substrate; an input matching network arranged on the substrate between the second terminal and the gate; and an output matching network arranged on the substrate between the drain and the first terminal, wherein the die further includes a closed-loop bias circuit coupled to the gate for biasing the power transistor based on a reference voltage applied to the closed-loop bias circuit, the closed-loop bias circuit including a sense circuit operable to sense an output current of the power transistor and an output circuit operable to bias the gate of the power transistor based on a difference between an output of the sense circuit and the reference voltage. 13. The assembly according to claim 12, wherein the first and second terminals comprise λ/4 transmission lines. 14. The assembly according to claim 12, further comprising a third terminal coupled to the closed-loop bias circuit for externally applying the reference voltage to the closed-loop bias circuit. 15. The assembly according to claim 12, wherein the input matching network comprises a capacitor arranged between the second terminal and the gate, wherein the closed-loop bias circuit is coupled to a node of the input matching network arranged between the second terminal and the capacitor for internally applying the reference voltage to the closed-loop bias circuit via the second terminal. 16. A method for manufacturing an RF power device assembly, comprising: providing a substrate; arranging on the substrate a die including a power transistor having a gate and drain and a closed-loop bias circuit for biasing the power transistor based on a reference voltage applied to the closed-loop bias circuit, the closed-loop bias circuit including a sense circuit for sensing an output current of the power transistor and an output circuit for biasing the gate of the power transistor based on a difference between an output of the sense circuit and the reference voltage; arranging an output matching network adjacent to the die on the substrate; arranging an input matching network adjacent to the die on the substrate; and coupling different nodes of the power transistor, closed-loop bias circuit, and matching networks via bond wires. 17. The method according to claim 16, further comprising: arranging a first terminal at least partly on the substrate; arranging a second terminal at least partly on the substrate; coupling the first terminal to the drain via bond wire couplings; and coupling the second terminal to the gate via further bond wire couplings. 18. The method according to claim 17, wherein the output matching network is arranged between the die and the first terminal. 19. The method according to claim 17, wherein the input matching network is arranged between the die and the second terminal. 20. The method according to claim 16, wherein the input matching network comprises a capacitor, and the method comprises coupling the closed-loop bias circuit to a node of the input matching network arranged between the second terminal and the capacitor for internally applying the reference voltage to the closed-loop bias circuit through the second terminal. 21. The method according to claim 16, further comprising: arranging a third terminal at least partially on the substrate; and coupling the third terminal to the closed-loop bias circuit for externally applying the reference voltage to the closed-loop bias circuit. 22. A method of manufacturing a bias circuit for an RF power transistor, comprising: integrating a closed-loop bias circuit on a power transistor die having a power transistor including a gate and drain, the closed-loop bias circuit including a sense circuit for sensing an output current of the power transistor and an output circuit for biasing the gate of the power transistor based on a difference between an output of the sense circuit and a reference voltage; arranging the die on a substrate; arranging an output matching network and an input matching network on the substrate; and coupling different nodes of the closed-loop bias circuit, power transistor and matching networks via bond wires. 23. A method of using an RF power transistor, comprising: coupling an output matching network to a drain of a power transistor; coupling an input matching network to a gate of the power transistor; coupling the gate and the drain to a closed-loop bias circuit integrated with the power transistor on the same die; and biasing the gate based on a reference voltage applied to the closed-loop bias circuit the closed-loop bias circuit including a sense circuit for sensing an output current of the power transistor and an output circuit for biasing the gate of the power transistor based on a difference between an output of the sense circuit and the reference voltage. 24. The method according to claim 23, wherein coupling the gate and the drain to the closed-loop bias circuit comprises: coupling the drain to the sense circuit; and coupling the gate to the output circuit.
이 특허에 인용된 특허 (2)
-
Birkbeck,John David, Bias circuit for a bipolar transistor.
-
Perugupalli, Prasanth; Lopuch, Stan; Dixit, Nagaraj V., Semiconductor power device and RF signal amplifier.
이 특허를 인용한 특허 (2)
-
Ridgers, Timothy John; Praamsma, Louis, Bias circuit for a transistor amplifier.
-
Parker, Eric G., Collapsible personal trolley.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.