초록 ▼

A packet including data and a cyclic redundancy check code is encoded by using a selectable one of N scrambling codes (N>1). The encoded packet is transmitted and received, then decoded N times by using the N scrambling codes. The cyclic redundancy check code is used to decide which one of the

A packet including data and a cyclic redundancy check code is encoded by using a selectable one of N scrambling codes (N>1). The encoded packet is transmitted and received, then decoded N times by using the N scrambling codes. The cyclic redundancy check code is used to decide which one of the N scrambling codes enabled the encoded packet to be decoded correctly, and the correctly decoded data are used. Packets with different formats, in particular with headers of different lengths, can be distinguished by the use of different scrambling codes, so that different formats can be employed without the need to transmit extra data to indicate which format has been used.

대표청구항 ▼

What is claimed is: 1. A data transmitting apparatus, comprising: a CRC inserter for adding a CRC code to input data to create a packet; a scrambling code generator for generating either a first scrambling code or a second scrambling code as selected by a control signal; an encoder using the scramb

What is claimed is: 1. A data transmitting apparatus, comprising: a CRC inserter for adding a CRC code to input data to create a packet; a scrambling code generator for generating either a first scrambling code or a second scrambling code as selected by a control signal; an encoder using the scrambling code generated by the scrambling code generator to encode the packet created by the CRC inserter; and a transmitting unit for transmitting the encoded packet, wherein the scrambling code generator comprises: a linear feedback shift register generating a cyclic code according to a predetermined generator polynomial; and a length counter for counting bits of the encoded packet and resetting the linear feedback shift register to a predetermined initial value after either a first number of bits or a second number of bits as selected by the control signal; and wherein the first scrambling code includes the first number of bits output from the linear feedback shift register and the second scrambling code includes the second number of bits output from the linear feedback shift register. 2. A data transmitting apparatus, comprising: a CRC inserter for adding a CRC code to input data to create a packet; a scrambling code generator for generating either a first scrambling code or a second scrambling code as selected by a control signal; an encoder using the scrambling code generated by the scrambling code generator to encode the packet created by the CRC inserter; and a transmitting unit for transmitting the encoded packet, wherein the scrambling code generator comprises: a linear feedback shift register generating a cyclic code according to a predetermined generator polynomial; and a length counter for counting bits of the encoded packet and resetting the linear feedback shift register to either a first initial value or a second initial value, as selected by the control signal, after a predetermined number of bits; and wherein the first scrambling code includes the predetermined number of bits output from the linear feedback shift register. 3. A data transmitting apparatus, comprising: a CRC inserter for adding a CRC code to input data to create a packet; a scrambling code generator for generating either a first scrambling code or a second scrambling code as selected by a control signal; an encoder using the scrambling code generated by the scrambling code generator to encode the packet created by the CRC inserter; and a transmitting unit for transmitting the encoded packet, wherein the scrambling code generator comprises: a linear feedback shift register generating a cyclic code according to a predetermined generator polynomial; and a length counter for counting bits of the encoded packet and resetting the linear feedback shift register to either a first initial value after a first number of bits or a second initial value after a second number of bits, as selected by the control signal; and wherein the first scrambling code includes the first number of bits output from the linear feedback shift register and the second scrambling code includes the second number of bits output from the linear feedback shift register. 4. A data receiving apparatus comprising: a receiving unit for receiving an encoded packet including a CRC code; a first code generator for generating a first scrambling code; a second code generator for generating a second scrambling code; a first decoder for decoding the received encoded packet by using the first scrambling code to obtain a first decoded packet; a second decoder for decoding the received encoded packet by using the second scrambling code to obtain a second decoded packet; a first checker for using the CRC code to detect errors in the first decoded packet; a second checker for using the CRC code to detect errors in the second decoded packet; and a decision unit for deciding, from results of error detection by the first checker and the second checker, whether any one of the first decoded packet and the second decoded packet was decoded correctly. 5. The receiving apparatus of claim 4, wherein: the first decoder is an exclusive-OR gate taking a bit-wise exclusive logical OR of the first scrambling code and the received packet; the second decoder is an exclusive-OR gate taking a bit-wise exclusive logical OR of the second scrambling code and the received packet. 6. The receiving apparatus of claim 4, wherein: the first code generator has a first linear feedback shift register generating a cyclic code according to a predetermined generator polynomial, and a first length counter for counting bits of the encoded packet and resetting the first linear feedback shift register to a predetermined initial value after a first number of bits, the first scrambling code including the first number of bits output from the first linear feedback shift register; and the second code generator has a second linear feedback shift register generating a cyclic code according to the predetermined generator polynomial, and a second length counter for counting bits of the encoded packet and resetting the second linear feedback shift register to the predetermined initial value after a second number of bits, the second scrambling code including the second number of bits output from the second linear feedback shift register. 7. The receiving apparatus of claim 4, wherein: the first code generator has a first linear feedback shift register generating a cyclic code according to a predetermined generator polynomial, and a first length counter for counting bits of the encoded packet and resetting the first linear feedback shift register to a first initial value after a predetermined number of bits, the first scrambling code including the predetermined number of bits output from the first linear feedback shift register; and the second code generator has a second linear feedback shift register generating a cyclic code according to the predetermined generator polynomial, and a second length counter for counting bits of the encoded packet and resetting the second linear feedback shift register to a second initial value after the predetermined number of bits, the second scrambling code including the predetermined number of bits output from the second linear feedback shift register. 8. The receiving apparatus of claim 4, wherein: the first code generator has a first linear feedback shift register generating a cyclic code according to a predetermined generator polynomial, and a first length counter for counting bits of the encoded packet and resetting the first linear feedback shift register to a first initial value after a first number of bits, the first scrambling code including the first number of bits output from the first linear feedback shift register; and the second code generator has a second linear feedback shift register generating a cyclic code according to the predetermined generator polynomial, and a second length counter for counting bits of the encoded packet and resetting the second linear feedback shift register to a second initial value after a second number of bits, the second scrambling code including the second number of bits output from the second linear feedback shift register. 9. A data receiving apparatus comprising: a receiving unit for receiving an encoded packet including a CRC code; a plurality of code generators for generating different scrambling codes; a plurality of decoders for decoding the received encoded packet by using the different scrambling codes to obtain a plurality of decoded packets; a plurality of checkers for using the CRC code to detect errors in the decoded packets; and a decision unit for deciding, from results of error detection by the plurality of checkers, whether any one of the decoded packets was decoded correctly.