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A calibration circuit calibrates an adjustable capacitance of a circuit having a time constant depending on the adjustable capacitance. The calibration circuit outputs a calibration signal carrying information for calibrating the capacitor and includes a calibration loop. The calibration circuit inc

A calibration circuit calibrates an adjustable capacitance of a circuit having a time constant depending on the adjustable capacitance. The calibration circuit outputs a calibration signal carrying information for calibrating the capacitor and includes a calibration loop. The calibration circuit includes: a controllable capacitance unit suitable to receive a control signal and including at least one array of switched capacitors that can be activated by the control signal, the unit being such as to output a first signal characterized by a parameter depending on the amount of capacitance of the array activated by the control signal; a comparison unit suitable to receive the first signal to assess whether the parameter meets a preset condition and to output a comparison signal representative of the assessment result; a control and timing logic unit suitable to receive the comparison signal to change this control signal based on the comparison signal, characterized in that the first signal is a logic signal and the parameter is a time parameter of the first signal.

대표청구항 ▼

What is claimed is: 1. A calibration circuit for calibrating an adjustable capacitance of a circuit having a time constant depending on said adjustable capacitance, the calibration circuit being adapted to output a calibration signal having information to calibrate said adjustable capacitance, the

What is claimed is: 1. A calibration circuit for calibrating an adjustable capacitance of a circuit having a time constant depending on said adjustable capacitance, the calibration circuit being adapted to output a calibration signal having information to calibrate said adjustable capacitance, the calibration circuit comprising: a calibration loop having: a controllable capacitance unit adapted to receive a control signal and including at least one array of switched capacitors that can be activated by the control signal, the controllable capacitance unit being adapted to output a first signal representing a parameter depending on an amount of capacitance of the array activated by the control signal; a comparison unit adapted to receive said first signal to assess whether said parameter meets a preset condition and to output a comparison signal representative of a result of said assessment; a control and timing logic unit adapted to receive the comparison signal and to change the control signal based on said comparison signal, wherein said first signal is a logic signal and said parameter is a time parameter of said first signal. 2. The calibration circuit according to claim 1 wherein the controllable capacitance unit includes a delay circuit with a delay controllable via the switched capacitor array, and wherein the time parameter is a delay of said first signal. 3. The calibration circuit according to claim 2 wherein the delay circuit is adapted to produce in the first signal, in response to a preset edge of a signal applied to its input, an edge having a delay depending on the amount of activated capacitance in the switched capacitor array. 4. The calibration circuit according to claim 2 wherein the delay circuit includes two delay stages, each including a respective switched capacitor array, the delay of the first signal being equal to a sum of two delays produced by the first and second stages, respectively. 5. The calibration circuit according to claim 2 wherein the comparison unit is adapted to check whether the delay is lower than a known half-period of a clock signal. 6. The calibration circuit according to claim 5 wherein the comparison unit includes a D flip-flop having: a data input terminal adapted to receive the first signal; a control input terminal adapted to receive the clock signal; and an output terminal adapted to output, based on the first signal and based on the control signal, the comparison signal. 7. The calibration circuit according to claim 1 wherein the control and timing logic unit includes a Successive Approximation Register and is adapted to change the control signal, during a calibration cycle with several sequential steps, by use of a successive approximation research strategy. 8. A system, comprising: a circuit having an adjustable capacitance adapted to adjust a time constant of said circuit; and a calibration circuit coupled to said circuit having the adjustable capacitance and adapted to provide a calibration signal to said circuit to adjust said adjustable capacitance, the calibration circuit including: a controllable capacitance unit to receive a control signal adapted to activate an amount of capacitance of the controllable capacitance unit, the controllable capacitance unit being adapted to output a first signal representing a time parameter that depends on an amount of capacitance of the array activated by the control signal; a comparison unit coupled to said controllable capacitance unit to receive said first signal and adapted to assess whether said time parameter meets a condition and to output a comparison signal representative of a result of said assessment; and a control and timing logic unit coupled to said comparison unit and adapted to receive the comparison signal and to change the control signal based on said comparison signal, wherein a value of said control signal after an end of a calibration cycle corresponds to a value of said calibration signal, provided by said control and timing logic unit to said circuit having the adjustable capacitance. 9. The system according to claim 8 wherein the circuit having an adjustable capacitance includes a filter having a cut-off frequency depending on the adjustable capacitance. 10. The system according to claim 8 wherein said circuit and said calibration circuit are part of a same integrated circuit. 11. The system according to claim 8 wherein said controllable capacitance unit includes: an array of switched capacitors controllable responsive to said control signal to provide said amount of capacitance; and a delay circuit coupled to said array and responsive to said amount of capacitance to provide a delay, of said first signal, corresponding to said time parameter. 12. The system according to claim 11 wherein said condition corresponds to whether said delay is lower than a half-period of a clock signal. 13. The system according to claim 8 wherein said comparison unit includes a flip-flop having: a first terminal adapted to receive the first signal; a second terminal adapted to receive the clock signal; and a third terminal adapted to output, based on the first signal and based on the control signal, the comparison signal. 14. A method to calibrate an adjustable capacitance of a circuit having a time constant depending on said adjustable capacitance, the method comprising: providing a control signal to activate an amount of capacitance and outputting a first signal representing a time parameter that depends on an amount of capacitance activated by the control signal; determining whether said time parameter meets a condition and outputting a comparison signal representative of a result of said determination; using said comparison signal to change the control signal, until an end of a calibration cycle is reached wherein a value of said control signal corresponds to a value of said calibration signal; and providing said calibration signal to said circuit having the adjustable capacitance to adjust the adjustable capacitance. 15. The method of claim 14 wherein providing said control signal to activate said amount of capacitance includes using said control signal to control an array of switched capacitors that provides said capacitance, and wherein outputting said first signal representing said time parameter includes providing a delay that corresponds to said activated amount of capacitances. 16. The method of claim 15 wherein said condition corresponds to whether said delay is lower than a half-period of a clock signal. 17. The method of claim 14 wherein providing said calibration signal to said circuit includes providing said calibration signal to a filter.