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Method and apparatus for semiconductor processing 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B65G-049/07
출원번호 UP-0929357 (2007-10-30)
등록번호 US-7748944 (2010-07-26)
발명자 / 주소
  • Price, JB
  • Keller, Jed
  • Dulmage, Laurence
  • Cheng, David
출원인 / 주소
  • Crossing Automation, Inc.
대리인 / 주소
    Martine Penilla & Gencarella, LLP
인용정보 피인용 횟수 : 6  인용 특허 : 52

초록

A method and apparatus for semiconductor processing is disclosed. In one embodiment, a method of transporting a wafer within a cluster tool, comprises placing the wafer into a first segment of a vacuum enclosure, the vacuum enclosure being attached to a processing chamber and a factory interface. Th

대표청구항

We claim: 1. A method of transporting a wafer within a plurality of cluster tools, comprising: placing the wafer into a first vacuum enclosure of a first cluster tool of the plurality of cluster tools, the first vacuum enclosure being connected to a first processing chamber and a factory interface;

이 특허에 인용된 특허 (52)

  1. Johnson Lester R. (411 Fourth St. Radford VA 24141), Apparatus for transferring semiconductor wafers.
  2. Ishii Katsumi (Fujino JPX) Mochizuki Yoshinori (Hachioji JPX), Arm apparatus for conveying semiconductor wafer and processing system using same.
  3. Perlov Ilya ; Goder Alexey ; Gantvarg Eugene, Carousel wafer transfer system.
  4. Kyogoku Mitsusuke,JPX, Device and method for load locking for semiconductor processing.
  5. Yoo, Woo Sik, Forced convection assisted rapid thermal furnace.
  6. Yoo, Woo Sik, Gas-assisted rapid thermal processing.
  7. Yoo, Woo Sik, Integrated ashing and implant annealing method.
  8. Yoo Woo Sik, Lamp based scanning rapid thermal processing.
  9. Nakano, Hitoshi, Load-lock chamber and exposure apparatus using the same.
  10. Murdoch Steven (Palo Alto CA), Method and apparatus for handling semiconductor wafers.
  11. Hassan Javathu K. (Hopewell Junction NY) Mack Alfred (Poughkeepsie NY) Wojtaszek Michael R. (Poughkeepsie NY), Method and apparatus for handling workpieces.
  12. Wooding Michael J. (Sunnyvale CA) Cardema Rudolfo S. (San Jose CA) Ramiller Charles L. (Santa Clara CA), Method and system for loading wafers.
  13. Kudo Hideo (Fukushima-ken JPX) Uchiyama Isao (Fukushima-ken JPX) Kimura Yoshiharu (Nigata-ken JPX) Suzuki Morie (Fukushima-ken JPX) Tanakajima Takashi (Gunma-ken JPX), Method for handling or processing semiconductor wafers.
  14. van der Meulen,Peter, Methods and systems for handling a workpiece in vacuum-based material handling system.
  15. Kim, Ki-sang; Jeoung, Gyu-chan; Kwag, Gyu-hwan, Multi-chamber system having compact installation set-up for an etching facility for semiconductor device manufacturing.
  16. Fairbairn Kevin ; Sinha Ashok, Multideck wafer processing system.
  17. Grutzediek Hartmut,DEX ; Scheerer Joachim,DEX, Procedure and facility for handling and transport of wafers in ultra-clean rooms.
  18. Doering Kenneth ; Galewski Carl J. ; Gadgil Prasad N. ; Seidel Thomas E., Processing chamber for atomic layer deposition processes.
  19. Doering, Kenneth; Galewski, Carl J., Processing chamber for atomic layer deposition processes.
  20. Yoo Woo Sik, Resistively heated single wafer furnace.
  21. Martin R. Elliott ; Jeffrey C. Hudgens ; Chris Pencis ; Damon Cox, Robot for handling semiconductor wafers.
  22. Kakehi Yutaka (Hikari JPX), Semiconductor substrate transport system.
  23. Savage, Richard N.; Menagh, Frank S.; Carvalheira, Helder R.; Troiani, Philip A.; Cossentine, Dan L.; Vaughan, Eric R.; Mayer, Bruce E., Semiconductor wafer processing system with vertically-stacked process chambers and single-axis dual-wafer transfer system.
  24. Savage, Richard N.; Menagh, Frank S.; Carvalheira, Helder R.; Troiani, Philip A.; Cossentine, Dan L.; Vaughan, Eric R.; Mayer, Bruce E., Semiconductor wafer processing system with vertically-stacked process chambers and single-axis dual-wafer transfer system.
  25. Woo Sik Yoo, Single wafer annealing oven.
  26. Wiesler Mordechai (Lexington MA) Weiss Mitchell (Haverford PA), Straight line wafer transfer system.
  27. Suda Atsuhiko,JPX ; Toyoda Kazuyuki,JPX ; Makiguchi Issei,JPX ; Ozawa Makoto,JPX, Substrate processing apparatus.
  28. Yonemitsu Shuji,JPX ; Karino Toshikazu,JPX ; Yoshida Hisashi,JPX ; Watahiki Shinichiro,JPX ; Yoshida Yuji,JPX ; Shimura Hideo,JPX ; Sugimoto Takeshi,JPX ; Aburatani Yukinori,JPX ; Ikeda Kazuhito,JPX, Substrate processing apparatus.
  29. Adams Douglas R., Substrate processing apparatus with small batch load lock.
  30. Woo Sik Yoo, System and method for providing defect free rapid thermal processing.
  31. Madan Arun (Golden CO) Von Roedern Bolko (Wheat Ridge CO), Thin film deposition apparatus including a vacuum transport mechanism.
  32. Yasar Tugrul ; Robison Rodney Lee ; Deyo Daniel ; Zielinski Marian, Transport system for wafer processing line.
  33. Williams Owen P. (Phoenix AZ), Vacuum wafer transport and processing system and method using a plurality of wafer transport arms.
  34. Blum Rick ; Fairbairn Kevin ; Lane Christopher, Vertical dual loadlock chamber.
  35. Heidt Donald W. (Whitewright TX) Thompson Steve (Kalispell MT) Lund Worm (Seattle WA) Thompson Raymon F. (Kalispell MT) Beasley Larry M. (Austin TX), Vertical thermal processor for semiconductor wafers.
  36. Gadgil Prasad N. ; Seidel Thomas E., Vertically-stacked process reactor and cluster tool system for atomic layer deposition.
  37. Martin, John M.; Harrison, Arthur W.; Edwards, Allen D., Wafer boat elevator system and method.
  38. Zeakes, Jason S.; Haris, Clinton; Mautz, Karl E.; Hiatt, William Mark, Wafer carrier transport system for tool bays.
  39. Sik, Yoo Woo, Wafer processing apparatus.
  40. Flegal ; deceased Christopher (late of New City NY by Gisela H. Flegal ; legal representative), Wafer processing machine vacuum front end method and apparatus.
  41. Kuribayashi, Hiromitsu; Yoo, Woo Sik, Wafer processing method.
  42. Hiromitsu Kuribayashi JP; Woo Sik Yoo, Wafer processing system.
  43. Woo Sik Yoo, Wafer processing system.
  44. Kuribayashi, Hiromitsu; Yoo, Woo Sik, Wafer processing system including a robot.
  45. Wada Athushi (Tokyo JPX), Wafer transfer device.
  46. Harada Yasuhiro (Ome JPX) Karino Toshikazu (Higashimurayama JPX) Saito Ryoji (Tokyo JPX) Tometsuka Koji (Tokyo JPX) Izumi Shoichiro (Tokyo JPX), Wafer transfer mechanism in vertical CVD diffusion apparatus.
  47. Coad George L. (Lafayette CA) Shaw R. Howard (Palo Alto CA) Hutchinson Martin A. (Santa Clara CA), Wafer transfer system.
  48. Toshima Masato, Wafer transfer system and method of using the same.
  49. Wiesler Mordechai ; Weiss Mitchell, Wafer transfer system having vertical lifting capability.
  50. Shin Kwang-hee,KRX ; Lee Seung-kun,KRX, Wafer transfer system of semiconductor fabricating equipment using a serial number detecting device.
  51. Miller Kenneth C. (280 Easy St. ; #117 Mountain View CA 94043), Wafer transport device.
  52. Brooks Norman B. (Carlisle MA) Olmstead Michael M. (Bedford MA), Wafer transport system.

이 특허를 인용한 특허 (6)

  1. Talmer, Mark A., Fast swap dual substrate transport for load lock.
  2. van der Meulen, Peter, Mid-entry load lock for semiconductor handling system.
  3. van der Meulen, Peter, Semiconductor manufacturing systems.
  4. van der Meulen, Peter; Kiley, Christopher C; Pannese, Patrick D.; Ritter, Raymond S.; Schaefer, Thomas A., Semiconductor wafer handling and transport.
  5. van der Meulen, Peter; Kiley, Christopher C; Pannese, Patrick D.; Ritter, Raymond S.; Schaefer, Thomas A., Semiconductor wafer handling and transport.
  6. van der Meulen, Peter; Kiley, Christopher C.; Pannese, Patrick D.; Ritter, Raymond S.; Schaefer, Thomas A., Semiconductor wafer handling transport.
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